dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 16

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1628D1G25
Objective data sheet
10.2.3 Deserializer
10.2.4
10.2.5 Comma detection and word alignment
The auto-zero feature (bit HS_RX_EQ_AUTO_ZERO_EN in register HS_RX_EQ_CTRL;
see
common-mode of the received signal. This feature can be set manually. It uses an
external algorithm that controls the DAC1628D1G25 via the SPI bus.
Set two gains to control the high-frequency and low-frequency jumps of the data (bits
HS_RX_x_EQ_HF_GAIN[1:0] and HS_RX_0_EQ_IF_GAIN[2:0] of register
HS_RX_x_EQ_GAIN; see
The deserializer performs the incoming data clock recovery and also the serial-to-parallel
conversion. One global PLL provides the same reference clock to the 4 lanes. Set the PLL
using register HS_RX_CDR_DIV (see
As stated in the JESD204B specification, the transmitter and the receiver first have to
synchronize. This is achieved through the SYNC_OUT signals and a synchronization
pattern (K28.5 symbol). The receiver (DAC1628D1G25) first drives its SYNC_OUT
outputs. The synchronization pattern is continuously sent until the receiver deasserts the
SYNC_OUT signal.
The lane processing uses the sync patterns to synchronize the data stream, determine the
initial running disparity and extract the 10-bit word from the incoming data stream
(word alignment).
The DAC1628D1G25 also uses the SYNC_OUT signal during normal operation to
request a link reinitialization when the 10b/8b module loses synchronization.
The SYNC_OUT signal conforms to LVDS signaling. Its common-mode voltage and its
single-ended peak amplitude can be programmed using bits SET_SYNC_LVL[3:0] and
SYNC_SET_VCM[6:4] in register SYNC_CFG_CTRL (see
SYNC_OUT is asynchronous with the frame clock. There is no timing specification of the
CLKINP and the CLKINN input, but the DAC1628D1G25 design allows some flexibility in
term of the selection of rising edge or falling edge, and a DAC clock period delay.
This stage monitors the data stream for code characters (comma detection), decodes the
words to bytes (octets) and performs optional character replacement as part of frame/lane
alignment monitoring and correction. This module provides the required control signals to
the RX controller and ILA.
This module decodes the 10-bit words to 8-bit words (octets). The decoding table is
specified in the IEEE 802.3-2005 specification. During decoding, the disparity is
calculated according to the disparity rules mentioned in the same specification. The
Not-In-Table error (NIT) and Disparity Error (DISP) can be monitored using bits
DEC_NIT_ERR_LNx and DEC_DISP_ERR_LNx (register DEC_FLAGS; see
When the disparity counter is more than +2 or less than 2, an error is generated.
Synchronization and word alignment
Table
139) is enabled by default for the deserializer to adapt itself to the
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
Table
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
140).
Table
135).
DAC1628D1G25
Table
146).
© NXP B.V. 2011. All rights reserved.
Table
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93).