dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 111

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 138. HS_RX_CDR_EN registers (address 05h to 06h) bit description
Default values are shown highlighted.
Table 139. HS_RX_EQ_CTRL register (address 07h) bit description
Default values are shown highlighted.
Table 140. Equalizer gain registers (address 08h to 0Bh) bit description
Default values are shown highlighted.
DAC1628D1G25
Objective data sheet
Address Register
Bit
5
4
3
2
1
0
Address
08h
09h
Symbol
HS_RX_EQ_TST_DTY_EN
HS_RX_EQ_AUTO_ZERO_EN R/W
HS_RX_3_EQ_EN
HS_RX_2_EQ_EN
HS_RX_1_EQ_EN
HS_RX_0_EQ_EN
Register
HS_RX_0_EQ_GAIN 5 to 4
HS_RX_1_EQ_GAIN 5 to 4
Bit
1
0
Bit
2 to 0
2 to 0
Symbol
HS_RX_1_CDR_TRACK_
DATA_EN
HS_RX_0_CDR_TRACK_
DATA_EN
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Access
R/W
R/W
R/W
R/W
R/W
GAIN[2:0]
GAIN[1:0]
GAIN[2:0]
Symbol
HS_RX_0_EQ_HF_
GAIN[1:0]
HS_RX_0_EQ_IF_
HS_RX_1_EQ_HF_
HS_RX_1_EQ_IF_
Rev. 1.1 — 10 October 2011
Value
0
1
0
1
0
1
0
1
0
1
0
1
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Description
Equalizer duty cycle test
Equalizer auto zero mode
Equalizer of rx_ln3
Equalizer of rx_ln2
Equalizer of rx_ln1
Equalizer of rx_ln0
disabled (for all lanes)
enabled (for all lanes)
disabled (for all lanes)
enabled (for all lanes)
disabled (power-down)
enabled (active)
disabled (power-down)
enabled (active)
disabled (power-down)
enabled (active)
disabled (power-down)
enabled (active)
Access Value
R/W
R/W
Access Value
R/W
R/W
-
-
-
-
…continued
0
1
0
1
Description
sets hf-gain for rx_ln0 equalizer
sets if-gain for rx_ln0 equalizer
sets hf-gain for rx_ln1 equalizer
sets if-gain for rx_ln1 equalizer
DAC1628D1G25
Description
CDR_ln1 in pfd mode
(reference loop)
CDR_ln1 in data tracking mode
(normal mode)
CDR_ln0 in pfd mode
(reference loop)
CDR_ln0 in data tracking mode
(normal mode)
© NXP B.V. 2011. All rights reserved.
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