dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 67

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 72.
Default settings are shown highlighted.
Table 73.
DAC1628D1G25
Objective data sheet
Address
03h
04h
Bit
7
6
5
4
3
2
1
0
Symbol
WORD_SWP_LN3
WORD_SWP_LN2
WORD_SWP_LN1
WORD_SWP_LN0
SEL_RF_F10_LN3
SEL_RF_F10_LN2
SEL_RF_F10_LN1
SEL_RF_F10_LN0
Manual lock registers (address 03h to 04h) bit description
CA_CTRL register (address 05h) bit description
Register
MAN_LOCK_LN_1_0
MAN_LOCK_LN_3_2
Bit
7 to 4
3 to 0
7 to 4
3 to 0
All information provided in this document is subject to legal disclaimers.
Symbol
MAN_LOCK_LN1[3:0]
MAN_LOCK_LN0[3:0]
MAN_LOCK_LN3[3:0]
MAN_LOCK_LN2[3:0]
Rev. 1.1 — 10 October 2011
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
lane 3 bit swapping
lane 2 bit swapping
lane 1 bit swapping
lane 0 bit swapping
lane 3 sampling mode
lane 2 sampling mode
lane 1 sampling mode
lane 0 sampling mode
Access Value
R/W
R/W
dout_ca_ln3[7:0] = din_ca_ln3[7:0]
dout_ca_ln3[7:0] = din_ca_ln3[0:7]
dout_ca_ln2[7:0] = din_ca_ln2[7:0]
dout_ca_ln2[7:0] = din_ca_ln2[0:7]
dout_ca_ln1[7:0] = din_ca_ln1[7:0]
dout_ca_ln1[7:0] = din_ca_ln1[0:7]
dout_ca_ln0[7:0] = din_ca_ln0[7:0]
dout_ca_ln0[7:0] = din_ca_ln0[0:7]
din_ca_ln3 sampled at falling edge f10_ln3
din_ca_ln3 sampled at rising edge f10_ln3
din_ca_ln2 sampled at falling edge f10_ln2
din_ca_ln2 sampled at rising edge f10_ln2
din_ca_ln1 sampled at falling edge f10_ln1
din_ca_ln1 sampled at rising edge f10_ln1
din_ca_ln0 sampled at falling edge f10_ln0
din_ca_ln0 sampled at rising edge f10_ln0
0h
0h
0h
0h
DAC1628D1G25
Description
manual lock setting
synchronization word alignment
lane 1
manual lock setting
synchronization word alignment
lane 0
manual lock setting
synchronization word alignment
lane 3
manual lock setting
synchronization word alignment
lane 2
© NXP B.V. 2011. All rights reserved.
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