dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 21

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1628D1G25
Objective data sheet
10.4 Clock input
The SPI timing characteristics are given in the following table.
Table 10.
[1]
The DAC1628D1G25 incorporates one differential clock input, CLKINN/CLKINP.
Symbol
f
t
t
t
t
t
t
SCLK
w(SCLK)
su(SCS_N)
h(SCS_N)
su(SDIO)
h(SDIO)
w(RESET_N)
Fig 8.
Fig 9.
The RESET_N signal is not linked to the SPI interface but enable the reset of the registers to the default
values.
RESET_N
SCS_N
SCLK
SDIO
SPI timing diagram
LVDS clock configuration
SPI timing characteristics
Parameter
SCLK frequency
SCLK pulse width
SCS_N set-up time
SCS_N hold time
SDIO set-up time
SDIO hold time
RESET_N pulse width
All information provided in this document is subject to legal disclaimers.
50 %
50 %
50 %
Rev. 1.1 — 10 October 2011
t
w(RESET_N)
t
su(SDIO)
50 %
LVDS
t
su(SCS_N)
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Z
t
h(SDIO)
diff
= 100 Ω
[1]
Min
-
30
20
20
10
5
30
CLKINP
CLKINN
100 Ω
t
w(SCLK)
Typ
-
-
-
-
-
-
-
DAC1628D1G25
001aah021
LVDS
Max
15
-
-
-
-
-
-
© NXP B.V. 2011. All rights reserved.
t
h(SCS_N)
001aaj813
Unit
MHz
ns
ns
ns
ns
ns
ns
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