dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 42

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dac1628d1g25

Manufacturer Part Number
dac1628d1g25
Description
Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
Table 26.
Default values are shown highlighted.
Table 27.
Default values are shown highlighted.
DAC1628D1G25
Objective data sheet
Address
13h
14h
Address
15h
Register
DAC_B_OFFSET_LSB
DAC_B_OFFSET_MSB 7 to 0
Register
MUTE_CTRL_0
DAC digital offset registers (address 11h to 14h) bit description
DAC digital offset registers (address 15h to 17h) bit description
Bit
7 to 0
Bit
7
6 to 5
4
3
2 to 0
All information provided in this document is subject to legal disclaimers.
Symbol
DAC_B_OFFSET[7:0]
DAC_B_OFFSET[15:8]
Symbol
HOLD_DATA
CLIP_SEL[1:0]
CLIP_DET_EN
MUTE_EN
MUTE_RATE[2:0]
Rev. 1.1 — 10 October 2011
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Access Value
R/W
Access Value
R/W
…continued
-
-
0
1
00
01
10
11
0
1
0
1
000
001
010
100
101
110
111
DAC1628D1G25
Description
DAC B digital offset value
Description
mute control
controls the rate of the mute
feature at 1 GHz (values below
are approximate values for
1 GHz)
least significant 8 bits for DAC
B digital offset
most significant 8 bits for DAC
B digital offset
disables hold feature
enables hold feature
no mute action
mute on clip_det_a
mute on clip_det_b
mute on clip_det_a or
clip_det_b
disable clipping detection
enable clipping detection
disable mute feature
enable mute feature
~8 ns (immediate)
~125 ns
~500 ns
~1 s
~2 s
~4 s
~8 s
© NXP B.V. 2011. All rights reserved.
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