dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 14

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1628D1G25
Objective data sheet
SYNC_OUT
Fig 3.
lane#
The descrambler can be enabled or disabled.
JESD204B receiver
DES
10.2 JESD204B receiver
10b
BUFFERING
Configure the DAC1628D1G25 before operating. It features an SPI slave interface to
access the internal registers. Some of these registers also provide information about the
JESD204B interface status. Optionally, an interrupt capability can be programmed using
those registers to ensure ease of use of the device.
Because of the JESD204B standardization, the DAC1628D1G25 does not require any
adjustment from the Transmit Logic Device (TLD) to capture the input data streams. Some
autolock features can be monitored using the SPI registers.
A new NXP automute feature enables switching off of the RF output signal as a result of
various internal events occurring.
The DAC1628D1G25 requires supplies of both 3.3 V and 1.8 V. The 1.8 V supply has
separate digital and analog power supply pins.
The JESD204B defines the following parameters:
The variable delay (latency uncertainty) is the result of uncertainties and variation in
design implementations along the path between the transmit logic device and the
DAC1628D1G25. The Inter-Lane Alignment (ILA) module present in Digital Layer
Processing (DLP) realigns the input streams to the last data received.
Table 6.
[1]
[2]
Symbol
t
d
•
•
•
frame
clock
L is the number of lanes per link
M is the number of converters per device
F is the number of octets per frame clock period
D = guaranteed by design.
Frame clock cycle.
Parameter Conditions
delay time
10b
Digital layer processing latency
All information provided in this document is subject to legal disclaimers.
WORD
ALIGN
SYNC
AND
Rev. 1.1 — 10 October 2011
digital layer processing delay
10b
K-DETECT
10b/8b
RX CONTROLLER
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
8b
DESCRAMBLER
Test
D
[1]
DAC1628D1G25
8b
<tbd>
Min
Lane
configuration
extraction
8b
8b
8b
8b
-
Typ
© NXP B.V. 2011. All rights reserved.
Max
<tbd>
16b
16b
configuration
interface
aaa-000491
internal
Unit
cycle
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[2]