dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 72

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 80.
Table 81.
Default settings are shown highlighted.
DAC1628D1G25
Objective data sheet
Bit
2
1
0
Bit
7 to 6
5 to 4
3 to 2
1 to 0
Symbol
POL_LN2
POL_LN1
POL_LN0
Symbol
LANE_SEL_LN3[1:0]
LANE_SEL_LN2[1:0]
LANE_SEL_LN1[1:0]
LANE_SEL_LN0[1:0]
LANE_POLARITY register (address 0Dh) bit description
LANE_SELECT register (address 0Eh) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
Access
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Value
0
1
0
1
0
1
Value
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Description
lane 2 data polarity
lane 1 data polarity
lane 0 data polarity
Description
lane 3 data mapping
lane swapping occurs at the end of the DLP. All the
registers linked to lane 0/lane 1/lane 2/lane 3 refer
to the physical lanes, not the logical ones after
swapping.
lane 2 data mapping
lane 1 data mapping
lane 0 data mapping
…continued
no action
invert all data bits of lane 2
no action
invert all data bits of lane 1]
no action
invert all data bits of lane 0
physical lane 3 is mapped to internal lane 0
physical lane 3 is mapped to internal lane 1
physical lane 3 is mapped to internal lane 2
physical lane 3 is mapped to internal lane 3
physical lane 2 is mapped to internal lane 0
physical lane 2 is mapped to internal lane 1
physical lane 2 is mapped to internal lane 2
physical lane 2 is mapped to internal lane 3
physical lane 1 is mapped to internal lane 0
physical lane 1 is mapped to internal lane 1
physical lane 1 is mapped to internal lane 2
physical lane 1 is mapped to internal lane 3
physical lane 0 is mapped to internal lane 0
physical lane 0 is mapped to internal lane 1
physical lane 0 is mapped to internal lane 2
physical lane 0 is mapped to internal lane 3
DAC1628D1G25
© NXP B.V. 2011. All rights reserved.
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