dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 131

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 115. PAGE_ADDRESS register (address 1Fh) bit
Table 116. Page x09 register allocation map . . . . . . . . . .94
Table 117. Lane 2 configuration registers (address 10h
Table 118. Lane 3/lane 2 sample LSB/MSB registers
Table 119. Lane 3 configuration registers (address 10h
Table 120. LN32_SELECT register (address 1Eh) bit
Table 121. PAGE_ADDRESS register (address 1Fh) bit
Table 122. Page_x0A register allocation map . . . . . . . .101
Table 123. Register MAIN_CTRL (address 00h) . . . . . .103
Table 124. Register DCSMU_AUTO_CTRL (address
Table 125. DCSMU_AUTO_RT (address 02h) . . . . . . . .104
Table 126. Clock extension registers (address 04h to 05h)
Table 127. Register DCSMU_PREDIV (address 06h) . .104
Table 128. Register MISC_CTRL (address 0Bh) . . . . . .104
Table 129. LDS/MDS of I/Q DC levels registers
Table 130. TYPE_ID registers (address 1Bh to 1Eh)
Table 131. Register PAGE_ADD (address 1Fh) . . . . . . .105
Table 132. Page x10 register allocation map . . . . . . . . .107
Table 133. HS_REF_EN register (address 00h) bit
Table 134. HS_REF_POLY_TRIM register
Table 135. HS_RX_CDR_DIV register (address 02h)
Table 136. HS_RX_CDR_CP register(address 03h) bit
Table 137. HS_RX_CDR_LOOP register(address 04h)
Table 138. HS_RX_CDR_EN registers (address 05h
Table 139. HS_RX_EQ_CTRL register (address 07h)
Table 140. Equalizer gain registers (address 08h to 0Bh)
Table 141. Equalizer offset registers (address 0Ch
Table 142. HS_RX_RT_VCM register (address 10h)
Table 143. HS_RX_RT_CTRL register (address 11h)
Table 144. Termination impedance fine-tuning (MSBs)
Table 145. HS_RX_X_RT_REFSIZE register
Table 146. SYNC_CFG_CTRL register (address 1Dh)
Table 147. PAGE_ADDRESS register (address 1Fh)
DAC1628D1G25
Objective data sheet
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
to 1Dh) bit description . . . . . . . . . . . . . . . . . . .97
(address 0Eh to 0Fh) bit description . . . . . . . .98
to 1Dh) bit description . . . . . . . . . . . . . . . . . . .98
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
bit description . . . . . . . . . . . . . . . . . . . . . . . .104
(address 0Ch to 0Fh) bit description . . . . . . .105
bit description . . . . . . . . . . . . . . . . . . . . . . . .105
description . . . . . . . . . . . . . . . . . . . . . . . . . . .109
(address 01h) bit description . . . . . . . . . . . . .109
bit description . . . . . . . . . . . . . . . . . . . . . . . .109
description . . . . . . . . . . . . . . . . . . . . . . . . . . .109
bit description . . . . . . . . . . . . . . . . . . . . . . . .109
to 06h) bit description . . . . . . . . . . . . . . . . . . 110
bit description . . . . . . . . . . . . . . . . . . . . . . . . 111
bit description . . . . . . . . . . . . . . . . . . . . . . . . 111
to 0Fh) bit description . . . . . . . . . . . . . . . . . . 112
bit description . . . . . . . . . . . . . . . . . . . . . . . . 113
bit description . . . . . . . . . . . . . . . . . . . . . . . . 113
registers (address 12h to 15h) bit description 114
(address 16h) bit description . . . . . . . . . . . . . 114
bit description . . . . . . . . . . . . . . . . . . . . . . . . 114
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Table 148. Page 11 register allocation map . . . . . . . . . . 115
Table 149. I_HS_REF_EN register (address 00h) bit
Table 150. I_HS_REF_POLY_TRIM register
Table 151. I_HS_RX_CDR_LOOP register(address
Table 152. I_HS_RX_CDR_EN registers (address
Table 153. I_HS_RX_EQ_CTRL register (address
Table 154. Equalizer offset registers (address 0Ch
Table 155. HS_RX_RT_CTRL register (address 11h)
Table 156. HS_RX monitor registers (address 19h
Table 157. HS_RX_IFIX_MON register (address 1Dh)
Table 158. HS_RX_VERSION register (address 1Eh)
Table 159. PAGE_ADDRESS register (address 1Fh)
Table 160. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 161. Revision history . . . . . . . . . . . . . . . . . . . . . . 126
bit description . . . . . . . . . . . . . . . . . . . . . . . . 114
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
(address 01h) bit description . . . . . . . . . . . . . 117
04h) bit description . . . . . . . . . . . . . . . . . . . . 117
05h to 06h) bit description . . . . . . . . . . . . . . . 118
07h) bit description . . . . . . . . . . . . . . . . . . . . 118
to 0Fh) bit description . . . . . . . . . . . . . . . . . . 119
bit description . . . . . . . . . . . . . . . . . . . . . . . . 120
to 1Ch) bit description . . . . . . . . . . . . . . . . . . 120
bit description . . . . . . . . . . . . . . . . . . . . . . . . 122
bit description . . . . . . . . . . . . . . . . . . . . . . . . 122
bit description . . . . . . . . . . . . . . . . . . . . . . . . 122
DAC1628D1G25
© NXP B.V. 2011. All rights reserved.
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