dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 104

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 125. DCSMU_AUTO_RT (address 02h)
Default values are shown highlighted.
Table 126. Clock extension registers (address 04h to 05h) bit description
Default values are shown highlighted.
Table 127. Register DCSMU_PREDIV (address 06h)
Default values are shown highlighted.
Table 128. Register MISC_CTRL (address 0Bh)
Default values are shown highlighted.
DAC1628D1G25
Objective data sheet
Bit
1
0
Address Register
04h
05h
Bit
7 to 0
Bit
7
6
5 to 4
Symbol
RESERVED
AUTO_CAL_RT
Symbol
DCMSU_PREDIVIDER[7:0]
Symbol
SR_CDI
RESERVED
I_LEV_CTRL[1:0]
RST_EXT_WCLK 7 to 0 RST_EXT_WCLK_TIME[7:0] R/W
RST_EXT_DCLK
Bit
7 to 0 RST_EXT_DCLK_TIME[7:0] R/W
Symbol
Access
R/W
R/W
Access
R/W
Access
R/W
R/W
R/W
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
Value
0
0
1
Value
-
Value
0
1
0
00
01
10
11
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Description
reserved
autocalibration termination resistance
Description
clock period
Description
CDI block software reset control
reserved
id data enable = 1: the normal operation;
if data enable = 0: digital signal processing
input = I_DC_LVL register value
predivider value for the DCMSU, expressed in WCLK
specifies output from CDI for I path
Access Value
disabled
enabled
8 bits for the predivider value
no action
perform a software reset on CDI
normal operation (CDI data output sent to digital
signal processing input)
digital signal processing input = I_DC_LVL
digital signal processing input = I_DC_LVL
-
-
DAC1628D1G25
Description
specify extension time reset,
expressed in WCLK clock period
specify extension time reset,
expressed in DCLK period
8 bits for the extension time
reset
8 bits for the extension time
reset
© NXP B.V. 2011. All rights reserved.
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