dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 13

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
10. Application information
DAC1628D1G25
Objective data sheet
10.1 General description
The DAC1628D1G25 is a dual 16-bit DAC operating up to 1.25 Gsps. A maximum input
data rate up to 625 Msps ensures more flexibility for wideband and multicarrier systems.
The incorporated quadrature modulator and 40-bit Numerically Controlled Oscillator
(NCO) simplifies the frequency selection of the system. This is also possible because of
the 2, 4 or 8 interpolation filters which remove undesired images.
The DAC1628D1G25 supports the following JESD204B key features:
The DAC1628D1G25 can be interfaced with any logic device that features high-speed
SERializer/DESerializer (SERDES) functionality. This macro is now widely available in
Field-Programmable Gate Array (FPGA) of different vendors. Standalone SERDES ICs
can also be used.
swapping to enhance the intrinsic board layout simplification of the JESD204B standard.
Each physical lane can be configured logically as lane 0, lane 1, lane 2 or lane 3.
This device is MCDA-ML compliant, offering inter-lane alignment between several
devices. An NXP proprietary mechanism in combination with the JESD204B subclass I
clause enables maintenance of sample alignment between devices up to output level.
Output samples are automatically aligned to the SYSREF signal generated by a dedicated
IC or by the FPGA itself. A system with several DAC1628D1G25s can produce data with a
guaranteed alignment of less than 1 DAC output clock period. The DAC1628D1G25
incorporates two differential SYSREF ports (located at the East and West side of the IC).
These can be programmed to act as an input or an output regarding the mode expected
for the system (Normal mode, Daisy chain). The device also enables independent link
reinitialization.
Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and
IOUTBP/IOUTBN, providing a nominal full-scale output current of 20 mA. An internal
reference is available for the reference current which is externally adjustable using pin
VIRES.
NXP includes polarity swapping for each of the lanes and additionally offers lane
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10-bit/8-bit decoding
Code group synchronization
Inter-Lane Alignment (ILA)
1 + x
Character replacement
TX/RX synchronization management via synchronization signals
Multiple Converter Device Alignment-Multiple Lanes (MCDA-ML) device
number L of serial lanes: 1, 2, 4
number M of data converters: 1 or 2
number F of octets per frame: 1, 2, 4
number S of samples per frame: 1, 2
14
+ x
15
All information provided in this document is subject to legal disclaimers.
scrambling polynomial
Rev. 1.1 — 10 October 2011
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
DAC1628D1G25
© NXP B.V. 2011. All rights reserved.
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