dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 106

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1628D1G25
Objective data sheet
Fig 31. Page x10: RX PHY control
10.17.8 Page x10/x11 : RX physical layer
PAGE x10: RX PHY / Page x11: RX PHY Monitoring *
VIN_P0
VIN_N0
VIN_P1
VIN_N1
VIN_P2
VIN_N2
VIN_P3
VIN_N3
HS_RX_1_RT_ENA* HS_RX_1_RT_HIZ*
HS_RX_2_RT_ENA* HS_RX_2_RT_HIZ*
HS_RX_3_RT_ENA* HS_RX_3_RT_HIZ*
HS_RX_0_RT_EN* HS_RX_0_RT_HIZ*
This page specifies the configuration ot the physical layer of the deserializer. Page x10
controls the various features as the equalizer and the common-mode voltage or resistor
termination. Page x11 monitors the status of the previous controls.
SYNC_SET_VCM
SYNC_SET_LVL
TERMINATION RESISTOR
TERMINATION RESISTOR
TERMINATION RESISTOR
TERMINATION RESISTOR
SYNC_EN
HS_RX_0_RT_REFSIZE
HS_RX_1_RT_REFSIZE
HS_RX_2_RT_REFSIZE
HS_RX_3_RT_REFSIZE
SYNC B
V
V
V
V
cm
cm
cm
cm
HS_RX_0_CDR_EN
HS_RX_1_CDR_EN
HS_RX_2_CDR_EN
HS_RX_3_CDR_EN
All information provided in this document is subject to legal disclaimers.
HS_REF_TUNE_EN*
HS_REF_CALIBRATE_EN*
HS_REF_EN*
HS_RX_RT_VCM_SEL*
HS_RX_RT_VCM_REF*
REFERENCES
HS_RX_0_EQ_IF_GAIN
HS_RX_1_EQ_IF_GAIN
HS_RX_2_EQ_IF_GAIN
HS_RX_3_EQ_IF_GAIN
Rev. 1.1 — 10 October 2011
HS_RX_2 _EQ_ENA*
HS_RX_1_EQ_EN*
HS_RX_3_EQ_EN*
HS_RX_0_EQ_EN
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
AUTO_ZERO
AUTO_ZERO
AUTO_ZERO
AUTO_ZERO
EQUALIZER
EQUALIZER
EQUALIZER
EQUALIZER
HS_RX_0_EQ_HF_GAIN
HS_RX_1_EQ_HF_GAIN
HS_RX_2_EQ_HF_GAIN
HS_RX_3_EQ_HF_GAIN
Registers followed by a * could be read back at the same
position (address and bits) on page x11 to check the
validation of the controlled action.
HS_RX_EQ_AUTO_ZERO_EN
DAC1628D1G25
HS_RX_CDR_DIVN
HS_RX_CDR_DIVM
HS_RX_CDR_LOW_SPEED_EN
10.N
M
(see page x01)
DCLK
© NXP B.V. 2011. All rights reserved.
aaa-000290
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