dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet
dac1628d1g25
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dac1628d1g25 Summary of contents
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... The DAC1628D1G25 is fully compliant with device subclass 1 of the JEDEC JESD204B standard, guaranteeing deterministic and repeatable interface latency using the differential SYSREF signal. The device also supports harmonic clocking to reduce system-level clock synthesis and distribution challenges ...
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... NXP Semiconductors The DAC1628D1G25 includes a 2, 4 or 8 clock multiplier which provides the appropriate internal clocks and an internal regulation to adjust the full-scale output current. The internal PLL can be bypassed to achieve the best possible noise performance at the analog outputs. The internal regulator adjusts the full-scale output current between 8.1 mA and 34 mA. The device is available in a HVQFN56 package (8 mm ...
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... Dual 16-bit DAC: JESD204B interface 1.25 Gsps Description plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; 8 8 0.85 mm All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Version SOT684-8 © NXP B.V. 2011. All rights reserved 133 ...
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Block diagram SYNC_OUTP DIGITAL LAYER PROCESSING SYNC_OUTN JESD204B VIN_P0 LANE L0 PROC VIN_N0 VIN_P1 LANE L1 PROC VIN_N1 VIN_P2 LANE L2 PROC VIN_N2 VIN_P3 LANE L3 PROC VIN_N3 JRES INTERRUPT CLOCK GENERATOR UNIT RF_ENABLE/IO1 MANAGMENT/ MONITORING IO0 FEATURES CLKIN_P ...
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... IO port bit enable pin (see Section automute 1.8 V digital power supply 11 G connect to ground 12 I/O Calibration resistor (12.5 k) for serial lanes termination All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 42 AUXBN 41 AUXBP 40 JTAG 39 RESET_N 38 SYSREF_E_P 37 SYSREF_E_N ...
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... V analog power supply 48 P 1.8 V PLL analog power supply 49 I/O DAC biasing resistor 50 I/O band gap input/output voltage 51 P 1.8 V PLL analog power supply All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved 133 ...
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... Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Min 0.5 0.5 0.5 0.5 0.5 55 40 40 Conditions ...
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... MDS; 2 JESD204B lanes f = 1228.8 Msps (p- 983.04 Msps (p- 620 Msps (p-p); All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Conditions Typ [2] 6 layers 15.9 [2] 8 layers 15.6 [2] 12 layers 14.0 amb ...
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... NCO < gpd |V | < gpd < gpd |V | < gpd D D All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 amb L Min Typ Max - 2272 - - <tbd> <tbd> <tbd> < ...
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... amb external D voltage = 1. auxiliary DAC A; I differential inputs auxiliary DAC B; I differential inputs All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 amb L Min Typ Max GND - 0.3V DDD(1V8) 0. ...
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... Msps (see Section 10.7.2) s coding register value = D 8000000000h register value = D F800000000h register value = D 0000000000h register value = D 0800000000h register value = D 7800000000h D All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 amb L Min Typ Max 1250 - 20 - ...
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... Msps 4 interpolation MHz at o 1 dBFS f = 983.04 Msps 4 interpolation 147 MHz at o 1 dBFS All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 amb L Min Typ Max - ...
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... Output samples are automatically aligned to the SYSREF signal generated by a dedicated the FPGA itself. A system with several DAC1628D1G25s can produce data with a guaranteed alignment of less than 1 DAC output clock period. The DAC1628D1G25 incorporates two differential SYSREF ports (located at the East and West side of the IC) ...
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... SPI registers. A new NXP automute feature enables switching off of the RF output signal as a result of various internal events occurring. The DAC1628D1G25 requires supplies of both 3.3 V and 1.8 V. The 1.8 V supply has separate digital and analog power supply pins. 10.2 JESD204B receiver ...
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... High impedance mode (register HS_RX_RT_CTRL; see AC-coupling is always required Fig 5. 10.2.2 Equalizer The DAC1628D1G25 embeds an internal equalizer (bits HS_RX_x_EQ_EN in register HS_RX_EQ_CTRL; see interference robustness between signals by amplifying the high-frequency jumps in the data conserving the energy of the low-frequencies ones. The equalizer can be programmed depending on the quality of the channel used (PCB traces/layout, connectors, etc ...
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... SYNC_SET_VCM[6:4] in register SYNC_CFG_CTRL (see SYNC_OUT is asynchronous with the frame clock. There is no timing specification of the CLKINP and the CLKINN input, but the DAC1628D1G25 design allows some flexibility in term of the selection of rising edge or falling edge, and a DAC clock period delay. 10.2.5 Comma detection and word alignment ...
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... INVALID: A code group that either shows a disparity error or that does not exist in the 10b/8b decoding table. The DAC1628D1G25 supports character replacement whatever the state of the descrambler. When descrambling is not active (bit DESCR_EN in register ILA_CTRL is set to logic 0; see previous sample. When descrambling is active (bit DESCR_EN is set to logic 1), the corresponding data octet D28 ...
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... K28.3 /A/ symbols have been received at a wrong position, a realignment takes place • if the buffers are empty or overflow, this is indicated by the registers ILA_BUF_ERR_LN0 to ILA_BUF_ERR_LN3 (see 10.2.8 Frame assembly The DAC1628D1G25 supports the following LMF configuration as described in the JESD204B standard (register LMF_CTRL; see Table 7. [ the number of samples per frame. [ the High-Density bit as described in the JESD204B specification ...
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... Fig 6. 10.3 Serial Peripheral Interface (SPI) 10.3.1 Protocol description The DAC1628D1G25 serial interface is a synchronous serial communication port allowing easy interfacing with many industry microprocessors. It provides access to the registers that define the operating modes of the chip in both Write mode and Read mode. This interface can be configured as a 3-wire type (SDIO as bidirectional pin 4-wire type (SDIO and SDO as unidirectional pin, input and output port respectively) ...
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... A1 A0 Read or Write mode access description 9, N1 and N0 indicate the number of bytes transferred after the instruction byte. Number of bytes transferred All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 ...
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... The RESET_N signal is not linked to the SPI interface but enable the reset of the registers to the default values. 10.4 Clock input The DAC1628D1G25 incorporates one differential clock input, CLKINN/CLKINP. Fig 9. DAC1628D1G25 Objective data sheet Dual 16-bit DAC: JESD204B interface 1.25 Gsps t w(RESET_N) ...
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... NXP Semiconductors Fig 10. Interfacing CML to LVDS The DAC1628D1G25 can operate with a clock frequency up to 500 MHz 1250 MHz if the internal PLL is bypassed. The clock input can be LVDS but it can also be interfaced with CML. Clock Domain Interface (CDI) logic handles the error free data transition from one internal clock domain to another ...
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... Figure 11. cos I sin sin Q cos All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Third interpolation filter Lower Upper Value - - - - - - - - - - - - - - - - - - - - - ...
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... Table 21). 20) can set the phase of the NCO. Equation -------------- 40 2 All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Path ...
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... OA fs 1024 DAC_A_DGAIN ----------------------------------------------- - = I 1 – 1024 All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Table 13. Value +1 4 +13 51 +610 Table DATA ------------------- ...
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... The output current of DAC B depends on the digital input data and the gain factor defined by bits DAC_B_DGAIN[11:0] of register DAC_B_DGAIN_LSB (see I IOUTBP I IOUTBN It is possible to define if the DAC1628D1G25 operates with a binary input or a two's complement input (bit CODING; see Table OA(fs) Table 14. ...
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... O fs 10.11 Digital offset adjustment When the DAC1628D1G25 analog output is DC connected to the next stage, the digital offset correction (bits DAC_A_OFFSET[15:0] and DAC_B_OFFSET[15:0]; see can be used to adjust the common-mode level at the output of each DAC. It adds an offset at the end of the digital part, just before the DACs. Following table shows the range of variation of the digital offset ...
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... V (p-p). 10.13 Auxiliary DACs The DAC1628D1G25 integrates two auxiliary DACs, which are used to compensate any offset between the DACs and the next stage in the transmission path. Both auxiliary DACs have a 10-bit resolution and are current sources (referenced to ground). ...
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... Auxiliary DAC transfer function AUX_A[9:2]/AUX_A[1:0]; AUX_B[9:0]/AUX_B[1:0] (binary coding) 00 0000 0000 ... 10 0000 0000 ... 11 1111 1111 DAC1628D IOUTAP/IOUTBP IOUTAN/IOUTBN All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 (mA) I AUXAP AUXBP AUXAN 0 2.2 ... ... 1.1 1.1 ... ... ...
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... NXP Semiconductors The DAC1628D1G25 can operate a differential output (p-p). In this configuration, connect the center tap of the transformer resistor, which is connected to the 3.3 V analog power supply. This adjusts the DC common-mode to around 2.7 V (see Fig 15 (p-p) differential output with transformer 10.15.2 IQ-modulator - BGX7100 interface The DAC1628D1G25 can be easily connected to the BGX7100 NXP IQ-modulator ...
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... NXP Semiconductors 10.15.3 IQ-modulator - DC interface When the system operation requires to keep the DC component of the spectrum, the DAC1628D1G25 can use a DC interface to connect an IQ-modulator. In this case, the offset compensation for local oscillator can be canceled using the digital offset control in the device. Figure 17 input level. ...
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... IOUTAP/IOUTBP IOUTAN/IOUTBN 634 Ω AUXAP/AUXBP AUXAN/AUXBN 442 Ω IOUTAP/IOUTAN IOUTBP/IOUTBN V = 2.75 V O(cm 1.96 V O(dif) All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 51.1 Ω 442 Ω 442 Ω BBAN/BBBN 698 Ω 698 Ω 51.1 Ω 51.1 Ω BBAP/BBAN BBBP/BBBN V = 1.7 V I(cm 1.23 V ...
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... The input common-mode level of the IQ-modulator • The range of offset correction 10.15.4 IQ-modulator - AC interface Use the DAC1628D1G25 AC-coupled when the IQ-modulator common-mode voltage is close to ground. The auxiliary DACs are required for local oscillator cancelation. Figure 21 input level and auxiliary DACs. IOUTAP/IOUTBP ...
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... V DDA(3V3) Use at least two capacitors for each power pin decoupling. Locate these capacitors as close as possible to the DAC1628D1G25 power pins. Use a separate LDO for the generation of the 1.8 V analog power (V digital power (V The die pad is used for both the power dissipation and electrical grounding. Insert several vias (typically 7 ...
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... INV_SINC_SEL MINUS_3DB pos.low.sideband neg.up.sideband neg.low.sideband FREQ_NCO PHI_NCO All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 PAGE x01: DUAL DAC CORE TEMPERATURE SENSOR power on/off sleep CLOCK DISTRIBUTION SYSREF MDS Managment EAST CLOCK GENERATION ...
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... CLIP CONFIG clip_det_b IGN_RFTX_EN DIRECT CONFIG SW_MUTE All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 ALARM_CFG HARD MUTE + MUTE_IQ HOLD MUTE + MUTE_IQ SOFT MUTE + MUTE_IQ SOFT MUTE DAT_IQ_VAL HARD MUTE + MUTE_IQ HOLD MUTE + MUTE_IQ ...
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Page x00 - register allocation map Table 17 shows an overview of all registers on page x00. Table 17. Page x00 register allocation map Address Register name R/W Bit 7 0 00h COMMON R/W 3W_SPI 1 01h TXCFG R/W ...
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Table 17. Page x00 register allocation map …continued Address Register name R/W Bit 7 15 0Fh DAC_OUT_CNTRL R 10h DAC_CLIPPING R/W 17 11h DAC_A_OFFSET_ R/W LSB 18 12h DAC_A_OFFSET_ R/W MSB 19 13h DAC_B_OFFSET_ R/W LSB 20 14h ...
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... All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved 133 ...
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... Symbol Access Value PH_CORR[7:0] R/W PH_CORR_EN R PH_CORR[12:8] All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Description interpolation no interpolation 2 interpolation 4 interpolation 8 interpolation - least significant 8 bits for the NCO phase offset - most significant 8 bits for the NCO phase offset ...
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... R/W - Bit Symbol DAC_A_OFFSET[7:0] DAC_A_OFFSET[15:8] All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Description DAC A digital gain control - least significant 8 bits for DAC A digital gain - most significant 4 bits for DAC A digital gain DAC B digital gain control ...
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... HOLD_DATA CLIP_SEL[1:0] 4 CLIP_DET_EN 3 MUTE_EN MUTE_RATE[2:0] All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 …continued Access Value Description R/W DAC B digital offset value - least significant 8 bits for DAC B digital offset - most significant 8 bits for DAC B digital offset ...
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... All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 …continued Access Value Description R/W 00 hard mute and mute_iq 01 hold mute and mute_iq 10 soft mute and mute_iq 11 soft mute 00 hard mute and mute_iq 01 hold mute and mute_iq ...
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... Access Value Description 0 Access Value Description R/W - page address All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved 133 ...
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... WCLK_PON PLL_BYP WCLK_DIV_BYP WCLK_DIV_SEL / 12 All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 DAC_A_GAIN TS_CLKDIV DCLK DAC_A_PON DAC A DAC_A_SLEEP AUX_DAC_A_PON AUX. AUX_DAC_A DAC TS_TOGGLE AUX_DAC_B_PON AUX. TS_FULL_RANGE ...
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Page x01 allocation map Table 30 shows an overview of all registers on page x01. Table 30. Page x01 register allocation map Address Register name R/W Bit 7 2 02h PLLCFG R/W PLL_BYP 4 04h WCLKGENCFG R/W DCLK_ MON_ ...
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Table 30. Page x01 register allocation map …continued Address Register name R/W Bit 7 28 1Ch DAC_A_AUX_LSB R/W AUX_DAC_ A_PON 29 1Dh DAC_B_AUX_MSB R/W 30 1Eh DAC_B_AUX_LSB R/W AUX_DAC_ B_PON 31 1Fh PAGE_ADDRESS R/W - Bit definition Bit 6 Bit ...
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... DAC clock / 4 011 wclk = DAC clock / 6 100 wclk = DAC clock / 12 110 wclk = DAC clock / 16 111 wclk = DAC clock / 24 All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved 133 ...
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... Access Value R/W - All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Description temperature sensor level selection usage depends on ts_mode: ts_mode = “00”: applied directly to temp_sensor ts_mode = “others”: sets threshold for temp_alarm Description sets clock frequency temp_sensor_cntrl ...
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... DAC_B_GAIN[7:0] R DAC_B_GAIN[9:8] R/W All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Description temperature sensor output (for use in raw mode) temp_actual > temp_threshold flag temp_actual (result of last measurement) Description maximum temp_actual found since last ts_rst_max Description minimum temp_actual found since last ts_rst_max ...
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... AUX_DAC_B[9:2] R/W 7 AUX_DAC_B_PD R AUX_DAC_B[1:0] Access Value R/W - All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Description - most significant 8 bits for auxiliary DAC A auxiliary DAC A power off - least significant 2 bits for auxiliary DAC A - most significant 8 bits for auxiliary ...
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Page x02: Multiple devices synchronization and interrupt This page specifies the configuration of the SYSREF signals (East and West) and how they are used for the multiple devices synchronization (MDS) feature. It also specifies the interrupts. 10.17.3.1 Page x02 ...
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Table 44. Page x02 register allocation map …continued Address Register name R/W 12 0Ch MDS_CNT_PRESET R/W 13 0Dh SYNC_LMFC_PE R/W 14 0Eh MDS_SYNC_CTRL R/W 16 10h MDS_DAISY_CYCLES R/W 17 11h MDS_WAIT_CYCLES R/W 19 13h ERR_RPT_CTRL R/W 20 14h ERR_RPT_POS R/W ...
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Table 44. Page x02 register allocation map …continued Address Register name R/W 28 1Ch INTR_FLAGS_1 R/W 31 15h PAGE_ADDRESS R/W [ undefined at power-up or after reset. Bit definition Bit 7 Bit 6 Bit 5 Bit 4 - ...
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... AND (dlp_sync) 01 dlp_issue (dlp_lock) 10 dlp_issue (dlp_sync) 11 R/W DLP/CDI-latency uncertainty correction 0 compensate for DLP/CDI-latency uncertainty 1 no correction for DLP/CDI-latency uncertainty All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved 133 ...
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... R/W NCO synchronization 0 disabled 1 enabled R/W NCO tuning manual control 0 disabled 1 enabled R/W MDS evaluation 0 disabled 1 enabled All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved 133 ...
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... R/W - delay offset for dataflow (two’s complement [16 to 15] All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 if MDS_MAN = 0 then initial value adjustment delay if MDS_MAN = 1 then controls adjustment delay © NXP B.V. 2011. All rights reserved 133 ...
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... Description R/W - number of digital clock periods required to synchronize daisy partner All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Description - determines MDS window LOW time - determines MDS window HIGH time © NXP B.V. 2011. All rights reserved 133 ...
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... DAC clock periods Access Value Description R/W - determines err_rpt position as related to LMFC Access Value Description R - actual value adjustment delay All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved 133 ...
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... R EQUAL R MDS_LOCK R EARLY_ERR R LATE_ERR R EQUAL_FOUND R MDS_ACTIVE All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Description early signal (sampled) from early-to-late detector 0 false 1 true late signal (sampled) from early-to-late detector 0 false 1 true equal signal (sampled) from ...
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... Bit Symbol Access Value INTR_EN[7:0] R INTR_EN[14:8] R/W All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 …continued Description adjustment delay error detection delay offset cannot be applied within available range MDS enable phase 00 ...
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... AUTO_DL_RDY 1 AUTO_CAL_RDY 0 FLAG_DL_ERR Access Value Description R/W - SPI page address All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Description - intr_dlp active indicates transition 1 mds_busy indicates transition 0 mds_busy indicates transition 0 temp_alarm indicates transition 0 ...
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... Lane controller 10b/8b decoder SR_CTRL_LN0 SR_DEC_LN0 SR_CTRL_LN1 SR_DEC_LN1 SR_CTRL_LN2 SR_DEC_LN2 SR_CTRL_LN3 SR_DEC_LN3 All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 SUP_LN_SYNC FRAME ASSEMBLY ILA ILA LANE 0 INIT_ILA_BUFPTR_LN0 REINIT_ILA_LN0 RESYNC_O_L_LN0 ILA LANE 1 INIT_ILA_BUFPTR_LN1 REINIT_ILA_LN1 RESYNC_O_L_LN1 ILA LANE 2 ...
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Page x03 allocation map Table 69 shows an overview of all registers on page x03. Table 69. Page x03 register allocation map Address Register name R/W Bit definition 00h SR_DLP_0 R/W SR_SWA_ LN3 1 01h SR_DLP_1 ...
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Table 69. Page x03 register allocation map …continued Address Register name R/W Bit definition 10h SOFT_RESET_ R/W - SCRAMBLER 17 11h INIT_SCR_S15T8 R/W _LN0 18 12h INIT_SCR_ R/W - S7T1_LN0 19 13h INIT_SCR_ R/W S15T8_LN1 20 14h ...
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... R/W soft reset inter-lane alignment 0 1 All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 soft reset sync_word_alignment lane 3 soft reset sync_word_alignment lane 2 soft reset sync_word_alignment lane 1 soft reset sync_word_alignment lane 0 soft reset clock_alignment lane 3 soft reset clock_alignment lane 2 ...
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... All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Access Value Description R/W 0h manual lock setting synchronization word alignment lane 1 0h manual lock setting synchronization word alignment lane 0 R/W 0h manual lock setting synchronization word alignment ...
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... R/W lane 0 scrambling mode 0 scrambling lane 0 depends on lock_ln0 and en_scr 1 scrambling lane 0 depends on man_scr_ln0 All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved 133 ...
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... R/W lane alignment mode 0 automatic lane alignment based on /A/ symbols 1 manual lane alignment based on man_align_lnx All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved 133 ...
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... R R All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Access Value Description 0h indicates alignment data-delay for lane 1 [1..15] 0h indicates alignment data-delay for lane 0 [1..15] 0h indicates alignment data-delay for lane 3 [1..15] 0h indicates alignment data-delay for lane 2 [1 ...
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... Access Value Description R/W lane 3 data polarity 0 no action 1 invert all data bits of lane 3 All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved 133 ...
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... All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved 133 ...
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... R/W BUFPTR_LN0[3:0] INIT_ILA_ R/W BUFPTR_LN3[3: INIT_ILA_ R/W BUFPTR_LN2[3:0] All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 no action soft_reset scrambler of lane 3 no action soft_reset scrambler of lane 2 no action soft_reset scrambler of lane 1 no action soft_reset scrambler of lane 0 Description 00h initialization value for lane 0 ...
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... K28.5 /K/ symbols R/W lane 0, resync over link 0 no action 1 lane 0 controller checks for K28.5 /K/ symbols All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved 133 ...
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... Description R/W - number of lanes [ R/W - number of converters [1] R/W - number of octets/frame [ Access Value Description R/W 0h page_address All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Table 110 and Table 116, 0E, 0F and 1E) © NXP B.V. 2011. All rights reserved 133 ...
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... K28_0_LN3 k28_5_ln3, k28_3_ln3, k28_0_ln3, RESET RST_KOUT_UNEXP_FLAGS RST_KOUT_FLAGS RST_DSIP_ERR_FLAGS RST_NIT_ERR_FLAGS All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 BER_MODE BER BER_LVL (I/Q DC levels used for BER test are specified on page x0A) DLP INTERRUPT INTR_CLR INTR_EN_NIT INTR_MODE: INTR_EN_DISP ...
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Page x04 allocation map description Table 89 shows an overview of all registers on page x04. Table 89. Page x04 register allocation map Address Register name R 00h ILA_MON_1_0 R 1 01h ILA_MON_3_2 R 2 02h ILA_BUFF_ERR ...
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Table 89. Page x04 register allocation map …continued Address Register name R 0Fh INTR_MISC_EN R/W INTR_BUFF _EN_CS_ INIT_LN3 16 10h FLAG_CNT_LSB R _LN0 17 11h FLAG_CNT_ R MSB_LN0 18 12h FLAG_CNT_LSB R _LN1 19 13h FLAG_CNT_ R MSB_LN1 ...
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Table 89. Page x04 register allocation map …continued Address Register name R 1Dh MON_FLAGS_ R/W RST_NIT_ RST ERR-FLAGS 30 1Eh DBG_CTRL R/W BER_MODE 31 1Fh PAGE_ R/W - ADDRESS [ undefined at power-up or after reset. ...
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... R - clock alignment phase monitor lane clock alignment phase monitor lane clock alignment phase monitor lane 0 All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Value Description - ila_buf_ln1 pointer - ila_buf_ln0 pointer - ila_buf_ln3 pointer - ila_buf_ln2 pointer © NXP B.V. 2011. All rights reserved. ...
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... K28_4_LN3 1 K28_3_LN3 0 K28_0_LN3 All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Description not-in-table error flag lane 3 not-in-table error flag lane 2 not-in-table error flag lane 1 not-in-table error flag lane 0 disparity error flag lane 3 ...
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... R action 1 generate interrupt if ILA_BUF_ERR_LN3 = 1 All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Description - lock_state monitor synchronization word alignment lane 1 - lock_state monitor synchronization word alignment lane 0 - lock_state monitor synchronization word alignment lane 3 ...
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... Access Value All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 …continued Description no action generate interrupt if ILA_BUF_ERR_LN2 = 1 no action generate interrupt if ILA_BUF_ERR_LN1 = 1 no action generate interrupt if ILA_BUF_ERR_LN0 = 1 Access Value Description R - LSBs of flag counter lane 0 ...
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... K symbols monitor flags 0 reset unexpected K symbols monitor flags R/W 0 reset K28_x monitor flags for lane 3 All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 no action detection unexpected K-character in ln<x> affects i_ln<x> no action detection K28_7 in ln<x> affects i_ln<x> no action detection K28_5 in ln<x> affects i_ln<x> ...
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... K symbol found unexpected K symbol found K28_7 (/F/) symbol found K28_5 (/K/) symbol found K28_3 (/A/) symbol found K28_0 (/R/) symbol found All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 …continued © NXP B.V. 2011. All rights reserved 133 ...
Page 86
... Dual 16-bit DAC: JESD204B interface 1.25 Gsps Definition looking for K28_5 (/K/) symbol four consecutive K28_5 (/K/) symbols have been received code group synchronization achieved not applicable All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved 133 ...
Page 87
... LN2_JESDV LN2_S CONFIG 9 LN2_HD LN2_CF CONFIG 10 LN2_RES1 CONFIG 11 LN2_RES2 CONFIG 12 LN2_FCHK CONFIG 13 All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 LANE 1 JESD204 CONFIGURATION LN1_DID LN1_ADJCNT LN1_BID LN1_ADJDIR LN1_LID LN1_PHADJ LN1_SCR LN1_L LN1_F LN1_K LN1_M LN1_CS LN1_N LN1_SUBCLASSV LN1_N’ ...
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Page x08 allocation map Table 110 shows an overview of all registers on page x08. Table 110. Page x08 register allocation map Address Register name R/W Bit definition b7 0 00h LN0_CFG_0 R 1 01h LN0_CFG_1 R 2 02h ...
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Table 110. Page x08 register allocation map …continued Address Register name R/W Bit definition b7 15 0Fh LN10_SAMPLE_ R MSB 16 10h LN1_CFG_0 R 17 11h LN1_CFG_1 R 18 12h LN1_CFG_2 13h LN1_CFG_3 R LN1_SCR 20 14h ...
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Table 110. Page x08 register allocation map …continued Address Register name R/W Bit definition b7 29 1Dh LN1_CFG_13 R 30 1Eh LN10_SEL W 31 1Fh PAGE_ADDRESS R undefined at power-up or after reset ...
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... R LN0_JESDV R LN0_S[4:0] R LN0_HD R LN0_CF[4:0] LN0_RES1[7:0] R LN0_RES2[7:0] R LN0_FCHK[7:0] R All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Description - lane 0 device ID - lane 0 adjustable counter - lane 0 bank ID - lane 0 lane ID - lane 0 adjustable direction lane 0 adjustable phase - number of lanes minus 1 - number of octets per frame ...
Page 92
... LN1_M[7:0] LN1_CS[1:0] LN1_N[4:0] LN1_SUBCLASSV[2:0] LN1_N’[4:0] LN1_JESDV LN1_S[4:0] All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Access Value Description R - internal DLP data on lane 0 or lane 1 depending on the value of LN10_SELECT (bit 1E; LSB) The data are strobed by DLP_STROBE (see 1D) ...
Page 93
... Access Value Description W specifies the lane affected by DLP_STROBE 0 1 Access Value Description R/W 0h page_address All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 …continued Access Value Description R - high density - number of control words per frame cycle R - lane 1 reserved field R - ...
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Page x09 allocation map description Table 116 shows an overview of all registers on page x09. Table 116. Page x09 register allocation map Address Register name R/W Bit definition b7 0 00h LN2_CFG_0 R 1 01h LN2_CFG_1 R 2 ...
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Table 116. Page x09 register allocation map …continued Address Register name R/W Bit definition b7 15 0Fh LN32_SAMPLE_ R MSB 16 10h LN3_CFG_0 R 17 11h LN3_CFG_1 R 18 12h LN3_CFG_2 13h LN3_CFG_3 R LN3_SCR 20 14h ...
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Table 116. Page x09 register allocation map …continued Address Register name R/W Bit definition b7 29 1Dh LN3_CFG_13 R 30 1Eh LN32_SELECT W 31 1Fh PAGE_ADDRESS R undefined at power-up or after reset ...
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... LN2_M[7:0] LN2_CS[1:0] LN2_N[4:0] LN2_SUBCLASSV[2:0] LN2_N’[4:0] LN2_JESDV LN2_S[4:0] LN2_HD LN2_CF[4:0] LN2_RES1[7:0] LN2_RES2[7:0] LN2_FCHK[7:0] All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Access Value Description R - lane 2 device lane 2 adjustable counter - lane 2 bank lane 2 adjustable direction ...
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... LN3_M[7:0] LN3_CS[1:0] LN3_N[4:0] LN3_SUBCLASSV[2:0] LN3_N’[4:0] LN3_JESDV LN3_S[4:0] All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Access Value Description R - internal DLP data on lane 2 or lane 3 depending on the value of LN10_SELECT (bit 1E; LSB) The data are strobed by DLP_STROBE (see 1D) ...
Page 99
... Access Value Description W specifies the lane affected by DLP_STROBE 0 1 Access Value Description R/W 0h page_address All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 …continued Access Value Description R - high density - number of control words per frame cycle R - lane 3 reserved field R - ...
Page 100
... CDI_MODE VIN_P2 ^2 mode mode VIN_N2 ^8 mode VIN_P3 Eq L3 VIN_N3 All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 IO_SEL_2 IO_SEL_0 FORCE_RST_DCLK RST_EXT_DCLK_TIME DCLK IO_SEL_1 (see page x01) CDI MON_DCLK_STOP MON_DCLK I_DC_LVL INTERFACE DAC DSP (see page x00) ...
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Page x0A register allocation map Table 122 shows an overview of all registers on page x0A. Table 122. Page_x0A register allocation map Address Register name R/W Bit 7 0 00h MAIN_CTRL R/W 1 01h DCSMU_AUTO_ R/W MAN_PON CTRL _CTRL ...
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Table 122. Page_x0A register allocation map …continued Address Register name R/W Bit 7 20 14h MON_DCLK R MON_ DCLK_ STOP 21 15h MON_DCLK_ R FLAGS 27 1Bh TYPE_ID_0 R 28 1Ch TYPE_ID_1 R 29 1Dh TYPE_ID_2 R 30 1Eh TYPE_ID_3 ...
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... R/W automatic lock detection 0 disabled 1 enabled R/W - reserved R/W automatic calibration equalizer 0 disabled (use auto-zero) 1 enabled All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved. 103 of 133 ...
Page 104
... I_DC_LVL register value 10 digital signal processing input = I_DC_LVL 11 digital signal processing input = I_DC_LVL All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Description specify extension time reset, expressed in WCLK clock period - 8 bits for the extension time reset ...
Page 105
... R Access Value R/W All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Description specifies output from CDI for Q path normal operation (CDI data output sent to digital signal processing input) id data enable = 1: the normal operation; if data enable = 0: digital signal processing ...
Page 106
... Registers followed could be read back at the same HS_RX_RT_VCM_SEL* position (address and bits) on page x11 to check the HS_RX_RT_VCM_REF* validation of the controlled action. All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 10.N DCLK M (see page x01) HS_RX_CDR_DIVN HS_RX_CDR_DIVM ...
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Page x10 register allocation map Table 132 shows an overview of all registers on page x10. Table 132. Page x10 register allocation map Address Register name R/W Bit 7 0 00h HS_REF_EN R 01h HS_REF_POLY_ R/W - ...
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Table 132. Page x10 register allocation map …continued Address Register name R/W Bit 7 13 0Dh HS_RX_1_EQ_ R/W - OFFSET 14 0Eh HS_RX_2_EQ_ R/W - OFFSET 15 0Fh HS_RX_3_EQ_ R/W - OFFSET 16 10h HS_RX_RT_VCM R 11h HS_RX_RT_ ...
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... Value R/W - R/W - R/W - All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Description hs_ref poly trimming inputs (actually not used) Description low speed mode disabled enabled divm ratio used to divide refclk (predivider) divn ratio used in CDR reference loop Description sets charge pump up-current (~0 8.0 ...
Page 110
... HS_RX_3_CDR_FACQ_EN 6 HS_RX_2_CDR_FACQ_EN 5 HS_RX_1_CDR_FACQ_EN 4 HS_RX_0_CDR_FACQ_EN 3 HS_RX_3_CDR_TRACK_ DATA_EN 2 HS_RX_2_CDR_TRACK_ DATA_EN All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Access Value Description R/W 0 CDR lane 3 disabled (power-down) 1 CDR lane 3 enabled (active) R/W 0 CDR of rx_ln2 disabled (power-down) 1 CDR of rx_ln2 enabled (active) ...
Page 111
... HS_RX_0_EQ_HF_ R/W GAIN[1: HS_RX_0_EQ_IF_ GAIN[2:0] HS_RX_1_EQ_HF_ R/W GAIN[1: HS_RX_1_EQ_IF_ GAIN[2:0] All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 …continued Access Value Description R/W 0 CDR_ln1 in pfd mode (reference loop) 1 CDR_ln1 in data tracking mode (normal mode) R/W 0 CDR_ln0 in pfd mode ...
Page 112
... SHORT HS_RX_2_EQ_OFFSET[5:0] 6 HS_RX_3_EQ_INPUT_ SHORT HS_RX_3_EQ_OFFSET[5:0] All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 …continued Description - sets hf-gain for rx_ln2 equalizer - sets if-gain for rx_ln2 equalizer - sets hf-gain for rx_ln3 equalizer - sets if-gain for rx_ln3 equalizer ...
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... R/W Termination of rx_ln2 0 disabled (power-down) 1 enabled (active) R/W Termination of rx_ln1 0 disabled (power-down) 1 enabled (active) R/W Termination of rx_ln0 0 disabled (power-down) 1 enabled (active) All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved. 113 of 133 ...
Page 114
... R/W - sets output levels (swing) of synchronization buffer Value Description - page address All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Description - most significant 8 bits of termination impedance fine-tuning lane 0 - most significant 8 bits of termination impedance fine-tuning lane 1 - most significant 8 bits of termination ...
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Page x11 register allocation map Table 148 shows an overview of all registers on page x11. Table 148. Page 11 register allocation map Address Register name R/W Bit 7 0 00h I_HS_REF_EN 01h I_HS_REF_POLY R - ...
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Table 148. Page 11 register allocation map …continued Address Register name R/W Bit 7 26 1Ah HS_RX_1_MON 1Bh HS_RX_2_MON 1Ch HS_RX_3_MON 1Dh HS_RX_IFIX_ R - MON 30 1Eh HS_RX_VERSION R 31 ...
Page 117
... Access Value R - Access Value R - All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Description hs_ref poly trimming inputs (actually not used) Description actual CDR loop resistance value © NXP B.V. 2011. All rights reserved. 117 of 133 ...
Page 118
... R Equalizer of rx_ln3 0 disabled (power-down) 1 enabled (active) All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Description 0 CDR of rx_ln3 disabled (power-down) 1 CDR of rx_ln3 enabled (active) 0 CDR of rx_ln2 disabled (power-down) 1 CDR of rx_ln2 enabled (active) ...
Page 119
... OFFSET[5:0] 6 HS_RX_2_EQ_INPUT_ SHORT HS_RX_2_EQ_ OFFSET[5:0] 6 HS_RX_3_EQ_INPUT_ SHORT HS_RX_3_EQ_ OFFSET[5:0] All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 …continued Access Value Description R rx_ln0 input equalizer shorted action 1 rx_ln0 equalizer input shorted ...
Page 120
... Access HS_RX_0_EQ_TST_DTY_ R OUT HS_RX_0_EQ_OFS_POL R HS_RX_0_LOCK_REF_ R CLK HS_RX_0_CDR_FACQ_ R BUSY All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 Value Description actual state hs_rx_0_eq_test_duty_out hs_rx_ln0 equalizer offset 0 negative 1 positive hs_rx_0 lock to reference clock 0 not locked to reference clock (pfd mode) ...
Page 121
... BUSY HS_RX_3_EQ_TST_DTY_ R OUT HS_RX_3_EQ_OFS_POL R HS_RX_3_LOCK_REF_ R CLK HS_RX_3_CDR_FACQ_ R BUSY All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 …continued Value Description actual state hs_rx_1_eq_test_duty_out hs_rx_ln1 equalizer offset 0 negative 1 positive hs_rx_1 lock to reference clock 0 not locked to reference clock (pfd mode) ...
Page 122
... Access Value Description - rx-phy version number Value Description - page address All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved. 122 of 133 ...
Page 123
... 8.1 6.45 8.1 6.45 8.0 6.30 8.0 6.30 0.5 6.5 6.5 7.9 6.15 7.9 6.15 References JEDEC JEITA - - - - - - All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 detail 0.5 0.4 0.1 0.05 0.05 0.1 0.3 European projection SOT684-8 c sot684-8_po Issue date 09-01-07 09-02-24 © NXP B.V. 2011. All rights reserved. ...
Page 124
... Negative Metal-Oxide Semiconductor Phase-Locked Loop Spurious-Free Dynamic Range Serial Peripheral Interface Wide band Code Division Multiple Access Wireless Local Loop All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved. 124 of 133 ...
Page 125
... DAC1628D1G25 Objective data sheet Dual 16-bit DAC: JESD204B interface 1.25 Gsps All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 ) — the ratio RBW . offset © NXP B.V. 2011. All rights reserved. ...
Page 126
... NXP Semiconductors 14. Revision history Table 161. Revision history Document ID Release date DAC1628D1G25 v.1.1 20111010 • Modifications: Section 1 “General description” • Section 2 “Features and benefits” • Section 3 “Applications” • Table 5 “Characteristics” DAC1628D1G25 v.1 20110907 DAC1628D1G25 Objective data sheet Dual 16-bit DAC: JESD204B interface 1.25 Gsps ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved. 127 of 133 ...
Page 128
... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved. 128 of 133 ...
Page 129
... Table 58. MDS_SYNC_CTRL register (address 0Eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 59. MDS_DAISY_CYCLES register (address 10h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 60. MDS_WAIT_CYCLES register (address 11h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59 All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 continued >> © NXP B.V. 2011. All rights reserved. 129 of 133 ...
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... Table 113. Lane 1 configuration registers (address 10h to 1Dh) bit description . . . . . . . . . . . . . . . . . . . 92 Table 114. LN10_SELECT register (address 1Eh) bit All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 continued >> © NXP B.V. 2011. All rights reserved. 130 of 133 ...
Page 131
... Table 159. PAGE_ADDRESS register (address 1Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 160. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 161. Revision history . . . . . . . . . . . . . . . . . . . . . . 126 All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 © NXP B.V. 2011. All rights reserved. 131 of 133 ...
Page 132
... Revision history . . . . . . . . . . . . . . . . . . . . . . 126 15 Legal information . . . . . . . . . . . . . . . . . . . . . 127 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . 127 15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 127 15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . 127 15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 128 16 Contact information . . . . . . . . . . . . . . . . . . . 128 All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 10 October 2011 DAC1628D1G25 continued >> © NXP B.V. 2011. All rights reserved. 132 of 133 ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 10 October 2011 Document identifier: DAC1628D1G25 ...