dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 118

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 152. I_HS_RX_CDR_EN registers (address 05h to 06h) bit description
Default values are shown highlighted.
Table 153. I_HS_RX_EQ_CTRL register (address 07h) bit description
Default values are shown highlighted.
DAC1628D1G25
Objective data sheet
Address
05h
06h
Bit
5
4
3
Symbol
HS_RX_EQ_TST_DTY_EN
HS_RX_EQ_AUTO_ZERO_EN R
HS_RX_3_EQ_EN
Register
HS_RX_CDR_EN_0
I_HS_RX_CDR_EN_1 3
Bit
3
2
1
0
2
1
0
Symbol
HS_RX_3_CDR_EN
HS_RX_2_CDR_EN
HS_RX_1_CDR_EN
HS_RX_0_CDR_EN
HS_RX_3_CDR_
TRACK_DATA_EN
HS_RX_2_CDR_
TRACK_DATA_EN
HS_RX_1_CDR_
TRACK_DATA_EN
HS_RX_0_CDR_
TRACK_DATA_EN
All information provided in this document is subject to legal disclaimers.
Access
R
R
Rev. 1.1 — 10 October 2011
Value
0
1
0
1
0
1
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Description
Equalizer duty cycle test
Equalizer auto zero mode
Equalizer of rx_ln3
disabled (for all lanes)
enabled (for all lanes)
disabled (for all lanes)
enabled (for all lanes)
disabled (power-down)
enabled (active)
Access Value
R
R
R
R
R
R
R
R
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC1628D1G25
Description
CDR of rx_ln3 disabled
(power-down)
CDR of rx_ln3 enabled (active)
CDR of rx_ln2 disabled
(power-down)
CDR of rx_ln2 enabled (active)
CDR of rx_ln1 disabled
(power-down)
CDR of rx_ln1 enabled (active)
CDR of rx_ln0 disabled
(power-down)
CDR of rx_ln0 enabled (active)
data tracking mode
CDR_ln3 in pfd mode
(reference loop)
CDR_ln3 in data tracking mode
(normal mode)
CDR_ln2 in pfd mode
(reference loop)
CDR_ln2 in data tracking mode
(normal mode)
CDR_ln1 in pfd mode
(reference loop)
CDR_ln1 in data tracking mode
(normal mode)
CDR_ln0 in pfd mode
(reference loop)
CDR_ln0 in data tracking mode
(normal mode)
© NXP B.V. 2011. All rights reserved.
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