dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 59
dac1628d1g25
Manufacturer Part Number
dac1628d1g25
Description
Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
Manufacturer
NXP Semiconductors
Datasheet
1.DAC1628D1G25.pdf
(133 pages)
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Table 60.
Default values are shown highlighted.
Table 61.
Default values are shown highlighted.
Table 62.
Default values are shown highlighted.
Table 63.
Default values are shown highlighted.
DAC1628D1G25
Objective data sheet
Bit
7 to 0
Bit
2 to 0
Bit
6 to 0
Bit
6 to 0
Symbol
MDS_WAIT_CYCLES[7:0]
Symbol
RPT_CTRL_ERR[2:0]
Symbol
RPT_POS_ERR[7:0]
Symbol
MDS_ADJ_DLY[6:0]
MDS_WAIT_CYCLES register (address 11h) bit description
RPT_CTRL_ERR register (address 13h) bit description
RPT_POS_ERR register (address 14h) bit description
MDS_ADJ_DLY register (address 15h) bit description
Access
R/W
Access
R/W
Access
R/W
Access
R
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
Value
-
Value
00x
010
011
100
101
110
111
Value
-
Value
-
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Description
Description
error reporting pulse width
Description
Description
actual value adjustment delay
number of daisy cycles required before releasing DLP
determines err_rpt position as related to LMFC
no error reporting pulse width
err_rpt_pulse_width = 2 DAC clock periods
err_rpt_pulse_width = 4 DAC clock periods
err_rpt_pulse_width = 8 DAC clock periods
err_rpt_pulse_width = 16 DAC clock periods
err_rpt_pulse_width = 32 DAC clock periods
err_rpt_pulse_width = 64 DAC clock periods
DAC1628D1G25
© NXP B.V. 2011. All rights reserved.
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