dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 117
dac1628d1g25
Manufacturer Part Number
dac1628d1g25
Description
Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
Manufacturer
NXP Semiconductors
Datasheet
1.DAC1628D1G25.pdf
(133 pages)
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NXP Semiconductors
Table 149. I_HS_REF_EN register (address 00h) bit description
Default values are shown highlighted.
Table 150. I_HS_REF_POLY_TRIM register (address 01h) bit description
Default values are shown highlighted.
Table 151. I_HS_RX_CDR_LOOP register(address 04h) bit description
Default values are shown highlighted.
DAC1628D1G25
Objective data sheet
Bit
2
1
0
Bit
5 to 0
Bit
7 to 5
Symbol
HS_RX_CDR_LOOP_RZ[2:0]
Symbol
HS_REF_TUNE_EN
HS_REF_CAL_EN
HS_REF_EN
Symbol
HS_REF_POLY_TRIM[5:0]
10.17.8.4 Page x11 bit definition detailed description
Access
R
R
R
All information provided in this document is subject to legal disclaimers.
Access
R
Rev. 1.1 — 10 October 2011
Value
0
1
0
1
0
1
Access
R
Value
-
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Description
continuous calibration mode
calibration mode
hs_ref module
Value
-
hs_ref is not in continuous calibration mode
hs_ref is in continuous calibration mode
hs_ref is not in calibration mode
hs_ref in calibration mode (when hs_ref_tune_en is low)
disabled (power-down)
enabled (active)
Description
hs_ref poly trimming inputs (actually not used)
Description
actual CDR loop resistance value
DAC1628D1G25
© NXP B.V. 2011. All rights reserved.
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