dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 114

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 144. Termination impedance fine-tuning (MSBs) registers (address 12h to 15h) bit description
Default values are shown highlighted.
Table 145. HS_RX_X_RT_REFSIZE register (address 16h) bit description
Default values are shown highlighted.
Table 146. SYNC_CFG_CTRL register (address 1Dh) bit description
Default values are shown highlighted.
Table 147. PAGE_ADDRESS register (address 1Fh) bit description
Default values are shown highlighted.
DAC1628D1G25
Objective data sheet
Address Register
12h
13h
14h
15h
Bit
3
2
1
0
Bit
7
6 to 4
3 to 0
Bit
4 to 0
Symbol
HS_RX_3_RT_REFSIZE
HS_RX_2_RT_REFSIZE
HS_RX_1_RT_REFSIZE
HS_RX_1_RT_REFSIZE
Symbol
SYNC_EN
SYNC_SET_VCM[6:4]
SYNC_SET_LVL[3:0]
Symbol
PAGE[4:0]
HS_RX_0_RT_REFSIZE
HS_RX_1_RT_REFSIZE
HS_RX_2_RT_REFSIZE
HS_RX_3_RT_REFSIZE
Access
R/W
Access
R/W
R/W
R/W
R/W
R/W
Access
R/W
R/W
Bit
7 to 0 HS_RX_0_RT_
7 to 0 HS_RX_1_RT_
7 to 0 HS_RX_2_RT_
7 to 0 HS_RX_3_RT_
-
Value
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Value
-
-
-
-
Symbol
REF_SIZE[8:1]
REF_SIZE[8:1]
REF_SIZE[8:1]
REF_SIZE[8:1]
Value
0
1
-
-
Rev. 1.1 — 10 October 2011
Description
least significant bit of termination impedance fine-tuning lane 3
least significant bit of termination impedance finetuning lane 2
least significant bit of termination impedance fine-tuning lane 1
least significant bit of termination impedance fine-tuning lane 0
page address
Description
Description
synchronization buffer
sets common-mode output voltage of synchronization buffer
sets output levels (swing) of synchronization buffer
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
disabled (power-down)
enabled (active)
Access Value
R/W
R/W
R/W
R/W
-
-
-
-
Description
most significant 8 bits of termination
impedance fine-tuning lane 0
most significant 8 bits of termination
impedance fine-tuning lane 1
most significant 8 bits of termination
impedance fine-tuning lane 2
most significant 8 bits of termination
impedance fine-tuning lane 3
DAC1628D1G25
© NXP B.V. 2011. All rights reserved.
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