dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 80

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 90.
Default settings are shown highlighted.
Table 91.
Default settings are shown highlighted.
Table 92.
Default settings are shown highlighted.
DAC1628D1G25
Objective data sheet
Address
00h
01h
Bit
3
2
1
0
Bit
7 to 6
5 to 4
3 to 2
1 to 0
Symbol
ILA_BUFF_ERR_LN3
ILA_BUFF_ERR_LN2
ILA_BUFF_ERR_LN1
ILA_BUFF_ERR_LN0
Symbol
CA_MON_LN3[1:0]
CA_MON_LN2[1:0]
CA_MON_LN1[1:0]
CA_MON_LN0[1:0]
10.17.5.2 Page x04 bit definition detailed description
ILA_MON registers (address 00h to 01h) bit description
ILA_BUFF_ERR register (address 02h) bit description
CA_MON register (address 03h) bit description
Register
ILA_MON_1_0
ILA_MON_3_2
The tables in this section contain detailed descriptions of the page x04 registers.
Bit
7 to 4
3 to 0
7 to 4
3 to 0
All information provided in this document is subject to legal disclaimers.
Symbol
ILA_MON_LN1[3:0]
ILA_MON_LN0[3:0]
ILA_MON_LN3[3:0]
ILA_MON_LN2[3:0]
Rev. 1.1 — 10 October 2011
Access
R
R
R
R
Access
R
R
R
R
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Value
0
1
0
1
0
1
0
1
Value
-
-
-
-
Access
R
R
Description
lane 3 ila buffer error
lane 2 ila buffer error
lane 1 ila buffer error
lane 0 ila buffer error
Description
clock alignment phase monitor lane 3
clock alignment phase monitor lane 2
clock alignment phase monitor lane 1
clock alignment phase monitor lane 0
ila_buf_ln3 pointer is in range
ila_buf_ln3 pointer is out of range
ila_buf_ln2 pointer is in range
ila_buf_ln2 pointer is out of range
ila_buf_ln1 pointer is in range
ila_buf_ln1 pointer is out of range
ila_buf_ln0 pointer is in range
ila_buf_ln0 pointer is out of range
Value
-
-
-
-
Description
ila_buf_ln1 pointer
ila_buf_ln0 pointer
ila_buf_ln3 pointer
ila_buf_ln2 pointer
DAC1628D1G25
© NXP B.V. 2011. All rights reserved.
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