dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 5

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dac1628d1g25

Manufacturer Part Number
dac1628d1g25
Description
Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
6. Pinning information
DAC1628D1G25
Objective data sheet
6.1 Pinning
6.2 Pin description
Table 2.
Symbol
AUXAP
AUXAN
CLKINP
CLKINN
SYSREF_W_P
SYSREF_W_N
VDDD(1V8)
IO0
RF_ENABLE/IO1
V
GND
JRES
Fig 2.
DDD(1V8)
Pin configuration
RF_ENABLE/IO1
Pin description
SYSREF_W_N
SYSREF_W_P
SYNC_OUTN
SYNC_OUTP
index area
terminal 1
V
V
All information provided in this document is subject to legal disclaimers.
DDD(1V8)
DDD(1V8)
CLKINP
CLKINN
AUXAN
AUXAP
JRES
GND
Pin
1
2
3
4
5
6
7
8
9
10
11
12
IO0
Rev. 1.1 — 10 October 2011
10
11
12
13
14
1
2
3
4
5
6
7
8
9
Type
O
O
I
I
I/O
I/O
P
O
I/O
P
G
I/O
[1]
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Description
auxiliary DAC A output current
complementary auxiliary DAC A output current
DAC clock positive input
DAC clock negative input
multiple devices synchronization positive signal, west side
multiple devices synchronization negative signal, west side
1.8 V digital power supply
IO port bit 0
IO port bit 1 or RF enable pin (see Section automute)
1.8 V digital power supply
connect to ground
Calibration resistor (12.5 k) for serial lanes termination
Transparent top view
DAC1628D1G25
DAC1628D1G25
42
41
40
39
38
37
36
35
34
33
32
31
30
29
aaa-000270
AUXBN
AUXBP
JTAG
RESET_N
SYSREF_E_P
SYSREF_E_N
V
SCS_N
SCLK
V
SDIO
SDO
n.c.
GND
DDD(1V8)
© NXP B.V. 2011. All rights reserved.
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