dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 71

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 79.
Default settings are shown highlighted.
Table 80.
DAC1628D1G25
Objective data sheet
Bit
7 to 5
4
3
2 to 0
Bit
3
Symbol
SEL_RE_INIT[2:0]
SYNC_POL
SYNC_INIT_LVL
SEL_SYNC[2:0]
Symbol
POL_LN3
SYNCOUT_MODE register (address 0Ch) bit description
LANE_POLARITY register (address 0Dh) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
Access
R/W
R/W
R/W
R/W
Access
R/W
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Value
000
001
010
011
100
101
110
111
0
1
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
other
Value
0
1
Description
reinitialization mode
synchronization polarity
synchronization initialization level
synchronization mode
Description
lane 3 data polarity
reinitialization request when 1 of the lane
resets is active
reinitialization request when rst_ln0 or rst_ln1 is
active
reinitialization request when rst_ln2 or rst_ln3 is
active
reinitialization request when rst_ln0 is active
reinitialization request when rst_ln1 is active
reinitialization request when rst_ln2 is active
reinitialization request when rst_ln3 is active
reinitialization request remains '0'
sync_out is active when LOW
sync_out is active when HIGH
synchronization starts with ‘0’
synchronization starts with ‘1’
synchronization when one of the four
lane_syncs is active
synchronization when all four lane_syncs are
active
synchronization when sync_ln0 or sync_ln1 is
active
synchronization when both sync_ln0 and sync_ln1
are active
synchronization when sync_ln2 or sync_ln3 is
active
synchronization when both sync_ln2 and sync_ln3
are active
synchronization when sync_ln0 is active
synchronization when sync_ln1 is active
synchronization when sync_ln2 is active
synchronization when sync_ln3 is active
synchronization remains fixed '1'
synchronization remains fixed '0'
no action
invert all data bits of lane 3
DAC1628D1G25
© NXP B.V. 2011. All rights reserved.
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