dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 15

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1628D1G25
Objective data sheet
10.2.1 Lane input
10.2.2 Equalizer
Each lane is Current Mode Logic (CML) compliant. It is terminated to a common voltage
with an integrated 50  resistor.
The common-mode voltage and the termination resistor can be programmed using
register HS_RX_RT_VCM (see
to 0x16; see
a High impedance mode (register HS_RX_RT_CTRL; see
AC-coupling is always required
The DAC1628D1G25 embeds an internal equalizer (bits HS_RX_x_EQ_EN in register
HS_RX_EQ_CTRL; see
interference robustness between signals by amplifying the high-frequency jumps in the
data conserving the energy of the low-frequencies ones. The equalizer can be
programmed depending on the quality of the channel used (PCB traces/layout,
connectors, etc.).
Fig 4.
Fig 5.
Lane input termination
AC-coupling
Table 144
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
and
data in +
data in −
Table
Table
153) in each high-speed serial lane. This improves the
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Table
145). When not used, the lane input buffer can be set to
Vin_p
Vin_n
V
50 Ω
DD1
142) and registers HS_RX_x_RT_REFSIZE (0x12
50 Ω
50 Ω
50 Ω
V
Z diff = 100 Ω
tt
Z tt
001aak166
DAC1628D1G25
V
50 Ω
DD2
001aak163
Table
50 Ω
143).
© NXP B.V. 2011. All rights reserved.
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