dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 55

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 45.
Default values are shown highlighted.
Table 46.
Default values are shown highlighted.
DAC1628D1G25
Objective data sheet
Bit
7 to 6
5
4
3
2 to 1
0
Bit
7 to 6
5
Symbol
MDS_EQ_CHECK[1:0]
MDS_MAN
MDS_SREF_DIS
MDS_EAST_WEST
MDS_MODE[1:0]
MDS_EN
Symbol
DLP_ISSUE_COND[1:0]
IGN_EN_CORR
10.17.3.2 Page x02 bit definition detailed description
MDS_MAIN register (address 00h) bit description
MDS_VS1_CTRL register (address 01h) bit description
The tables in this section contain detailed descriptions of the page x02 registers.
Access
R/W
R/W
R/W
R/W
R/W
R/W
Access
R/W
R/W
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
Value
00
01
10
11
0
1
0
1
0
1
00
01
10
11
0
1
Value
00
01
10
11
0
1
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Description
control adjustment delays
sref generation
MDS mode
MDS function control
Description
digital lane processing issue condition that generates
an error in the MDS module
DLP/CDI-latency uncertainty correction
lock mode
MDS input/output
lock when (early = 1 and late = 1)
lock when (early = 1, late = 1 and equal = 1)
lock when equal = 1
force lock (equal-check = 1)
auto-control adjustment delays
manual control adjustment delays
disabled
enabled
west used as MDS input
east used as MDS input
mds_vs0 all-slave mode
mds_vs0 master mode
mds_vs1 without daisy-chain control
mds_vs1 with daisy-chain control
disabled
enabled
dlp_issue  (dlp_lock) OR (dlp_sync)
dlp_issue  (dlp_lock) AND (dlp_sync)
dlp_issue  (dlp_lock)
dlp_issue  (dlp_sync)
compensate for DLP/CDI-latency uncertainty
no correction for DLP/CDI-latency uncertainty
DAC1628D1G25
© NXP B.V. 2011. All rights reserved.
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