dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 69

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 75.
Table 76.
DAC1628D1G25
Objective data sheet
Bit
6 to 5
4 to 2
1
0
Bit
5 to 2
1
0
Symbol
SEL_ILA[1:0]
SEL_LOCK[2:0]
SUP_LN_SYNC
DESCR_EN
Symbol
MSB_MAN_LOCK_LN[3:0]
DYN_ALIGN_EN
FORCE_ALIGN
ILA_CTRL register (address 07h) bit description
FORCE_ALIGN register (address 08h) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
Access
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Value
00
01
10
11
000
001
010
011
100
101
0
1
0
1
Value
-
0
1
0
1
Description
inter-lane alignment trigger mode
inter-lane alignment start mode
inter-lane alignment enable
data descrambling
Description
most significant 4 bits of man_lock_ln
dynamic realignment mode
lane alignment mode
inter-lane alignment is done after receiving
1 /A/-symbol
inter-lane alignment is done after receiving
2 /A/-symbols
inter-lane alignment is done after receiving
3 /A/-symbols
inter-lane alignment is done after receiving
4 /A/-symbols
inter-lane alignment can only start if all (4 or 2)
lanes are locked
inter-lane alignment can start if one of the (4 or 2)
lanes are locked
inter-lane alignment can start if lane 0 is locked
inter-lane alignment can start if lane 1 is locked
inter-lane alignment can start if lane 2 is locked
inter-lane alignment can start if lane 3 is locked
inter-lane alignment synchronization disabled
inter-lane alignment synchronization enabled
disabled
enabled
no dynamic realignment
dynamic realignment (and monitoring) enabled
automatic lane alignment based on
/A/ symbols
manual lane alignment based on man_align_lnx
DAC1628D1G25
© NXP B.V. 2011. All rights reserved.
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