dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 101

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

Table 122. Page_x0A register allocation map
Address Register name
0
1
2
4
5
6
7
11 0Bh
12 0Ch
13 0Dh
14 0Eh
15 0Fh
16 10h
17 11h
18 12h
00h
01h
02h
04h
05h
06h
07h
MAIN_CTRL
DCSMU_AUTO_
CTRL
DCSMU_AUTO_
RT
RST_EXT_WCLK
RST_EXT_DCLK
DCMSU_
PREDIVCNT
EHS_CTRL
MISC_CTRL
I_DC_LVL_LSB
I_DC_LVL_MSB
Q_DC_LVL_LSB
Q_DC_LVL_MSB
IO_MUX_CTRL0
IO_MUX_CTRL1
IO_MUX_CTRL2
10.17.7.1 Page x0A register allocation map
Table 122
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
shows an overview of all registers on page x0A.
MAN_PON
SR_CDI
_CTRL
Bit 7
-
-
OSC_TEST
RING_
Bit 6
POFF_RX[3:0]
-
-
-
Bit 5
-
-
IO_EN[1:0]
CTRL[1:0]
I_LVL_
RST_EXT_WCLK_TIME[7:0]
RST_EXT_DCLK_TIME[7:0]
DCMSU_PREDIVIDER[7:0]
LOCK_DET
FORCE_
Bit 4
Q_DC_LVL[15:8]
I_DC_LVL[15:8]
Q_DC_LVL[7:0]
IO_SEL_0[7:0]
-
I_DC_LVL[7:0]
IO_SEL_1[7:0]
IO_SEL_2[7:0]
Bit definition
NO_DCLK_
QUICK_
REINIT
AUTO_
Q_LEV_CTRL[1:0]
Bit 3
EN
-
IO_EHS[1:0]
AUTO_
LOCK_
DET_EN
REINIT
FULL_
Bit 2
-
RESERVED
RESERVED AUTO_CAL
RST_DCLK
FORCE_
Bit 1
CDI_MODE[1:0]
SDO_EHS[1:0]
FORCE_
CAL_EQ
AUTO_
WCLK
RST_
Bit 0
_RT
Default
Bin
0000
0011
0000
1100
0000
0000
0100
0000
0100
0000
0001
0000
0001
1010
0000
0000
0000
0000
1000
0000
0000
0000
1000
0000
1111
1111
1111
1111
1111
1111
Hex
03h
0Ch
00h
40h
40h
10h
1Ah
00h
00h
80h
00h
80h
FFh
FFh
FFh