dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 66

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 70.
Default settings are shown highlighted.
Table 71.
Default settings are shown highlighted.
DAC1628D1G25
Objective data sheet
Address
00h
01h
Bit
7
6
5
4
1
0
Symbol
FORCE_LOCK_LN3
FORCE_LOCK_LN2
FORCE_LOCK_LN1
FORCE_LOCK_LN0
FRAME_ALIGN_EN
SR_ILA
10.17.4.2 Page x03 bit definition detailed description
Soft reset DLP registers (address 00h to 01h) bit description
FORCE_LOCK register (address 02h) bit description
SR_DLP_1
Register
SR_DLP_0
The tables in this section contain detailed descriptions of the page x03 registers.
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SR_SWA_LN3
SR_SWA_LN2
SR_SWA_LN1
SR_SWA_LN0
SR_CA_LN3
SR_CA_LN2
SR_CA_LN1
SR_CA_LN0
SR_CTRL_LN3
SR_CTRL_LN2
SR_CTRL_LN1
SR_CTRL_LN0
SR_DEC_LN3
SR_DEC_LN2
SR_DEC_LN1
SR_DEC_LN0
Symbol
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
Access
R/W
R/W
R/W
R/W
R/W
R/W
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Access Value Description
R/W
R/W
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
lane 3 lock mode
lane 2 lock mode
lane 1 lock mode
lane 0 lock mode
frame alignment
soft reset inter-lane alignment
automatic lock sync_word_alignment lane 3
manual lock sync_word_alignment lane 3
automatic lock sync_word_alignment lane 2
manual lock sync_word_alignment lane 2
automatic lock sync_word_alignment lane 1
manual lock sync_word_alignment lane 1
automatic lock sync_word_alignment lane 0
manual lock sync_word_alignment lane 0
no action
enable frame alignment
no action
reset
soft reset sync_word_alignment lane 3
soft reset clock_alignment lane 3
soft reset clock_alignment lane 2
soft reset clock_alignment lane 1
soft reset clock_alignment lane 0
soft reset controller lane 3
soft reset decoder_10b8b lane 3
soft reset decoder_10b8b lane 2
soft reset decoder_10b8b lane 1
soft reset decoder_10b8b lane 0
soft reset sync_word_alignment lane 2
soft reset sync_word_alignment lane 1
soft reset sync_word_alignment lane 0
soft reset controller lane 2
soft reset controller lane 1
soft reset controller lane 0
DAC1628D1G25
© NXP B.V. 2011. All rights reserved.
66 of 133