dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 129

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
17. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. SPI timing characteristics . . . . . . . . . . . . . . . .21
Table 11. Interpolation filter coefficients . . . . . . . . . . . . . .22
Table 12. Complex modulator operation mode . . . . . . . .24
Table 13. Inversion filter coefficients . . . . . . . . . . . . . . . .25
Table 14. DAC transfer function . . . . . . . . . . . . . . . . . . .26
Table 15. Digital offset adjustment . . . . . . . . . . . . . . . . .27
Table 16. Auxiliary DAC transfer function . . . . . . . . . . . .29
Table 17. Page x00 register allocation map . . . . . . . . . .37
Table 18. Register COMMON (address 00h) bit
Table 19. Register TXCFG (address 01h) bit description 39
Table 20. NCO phase offset registers (address 02h
Table 21. NCO frequency registers (address 04h
Table 22. DAC output phase correction factor registers
Table 23. DAC digital gain control registers (address
Table 24. Register DAC_OUT_CTRL (address 0Fh) . . .41
Table 25. Register DAC_CLIPPING (address 10h) . . . . .41
Table 26. DAC digital offset registers (address 11h
Table 27. DAC digital offset registers (address 15h
Table 28. Register MUTE_AL_EN (address 18h) . . . . . .43
Table 29. PAGE_ADDRESS register (address 1Fh) bit
Table 30. Page x01 register allocation map . . . . . . . . . .46
Table 31. PLLCFG register (address 02h) bit description 48
Table 32. WCLKGENCFG register (address 04h) bit
Table 33. TEMPS_CTRL register (address 05h) bit
Table 34. TEMPS_LEVEL register (address 06h) bit
Table 35. TEMPS_CLKDIV register (address 07h) bit
Table 36. TEMPS_TIMER register (address 08h) bit
DAC1628D1G25
Objective data sheet
Read or Write mode access description . . . . .20
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .7
Thermal characteristics . . . . . . . . . . . . . . . . . . .7
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .8
Digital layer processing latency . . . . . . . . . . . .14
LMF configuration . . . . . . . . . . . . . . . . . . . . . .18
Number of bytes transferred . . . . . . . . . . . . . .20
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
to 03h) bit description . . . . . . . . . . . . . . . . . . .40
to 08h) bit description . . . . . . . . . . . . . . . . . . .40
(address 09h to 0Ah) bit description . . . . . . . .40
0Bh to 0Eh) bit description . . . . . . . . . . . . . . .41
to 14h) bit description . . . . . . . . . . . . . . . . . . .41
to 17h) bit description . . . . . . . . . . . . . . . . . . .42
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Table 37. TEMPS_OUT register (address 09h) bit
Table 38. TEMPS_MAX register (address 0Ah) bit
Table 39. TEMPS_MIN register (address 0Bh) bit
Table 40. DAC_PON_SLEEP register (address 16h)
Table 41. Analog gain control (address 17h to 1Ah)
Table 42. Auxiliary DACs registers (address 1Bh to 1Eh)
Table 43. PAGE_ADDRESS register (address 1Fh) bit
Table 44. Page x02 register allocation map . . . . . . . . . . 52
Table 45. MDS_MAIN register (address 00h) bit
Table 46. MDS_VS1_CTRL register (address 01h) bit
Table 47. MDS_IO_CTRL register (address 02h) bit
Table 48. MDS_MISC_CTRL0 register (address 03h)
Table 49. MDS_MAN_ADJUST_DLY register
Table 50. MDS_AUTO_CYCLES register (address
Table 51. MDS_MISC_CTRL1 register (address
Table 52. MDS_OFFSET_DLY register (address
Table 53. MDS window registers (address 08h
Table 54. LMFC_PERIOD register (address 0Ah) bit
Table 55. LMFC_PRESET register (address 0Bh) bit
Table 56. MDS_CNT_PRESET register (address
Table 57. SYNC_LMFC_PE register (address 0Dh) bit
Table 58. MDS_SYNC_CTRL register (address 0Eh)
Table 59. MDS_DAISY_CYCLES register (address 10h)
Table 60. MDS_WAIT_CYCLES register (address 11h)
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 51
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 56
(address 04h) bit description . . . . . . . . . . . . . . 57
05h) bit description . . . . . . . . . . . . . . . . . . . . . 57
06h) bit description . . . . . . . . . . . . . . . . . . . . . 57
07h) bit description . . . . . . . . . . . . . . . . . . . . . 57
to 09h) bit description . . . . . . . . . . . . . . . . . . . 58
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
0Ch) bit description . . . . . . . . . . . . . . . . . . . . . 58
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 58
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 58
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59
DAC1628D1G25
© NXP B.V. 2011. All rights reserved.
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