dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 130

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 61. RPT_CTRL_ERR register (address 13h) bit
Table 62. RPT_POS_ERR register (address 14h) bit
Table 63. MDS_ADJ_DLY register (address 15h) bit
Table 64. MDS_STATUS registers (address 16h to 17h)
Table 65. INTR_CTRL register (address 18h) bit
Table 66. INTR_EN registers (address 19h to 1Ah) bit
Table 67. INTR_FLAGS registers (address 19h to 1Ah)
Table 68. PAGE_ADDRESS register (address 1Fh) bit
Table 69. Page x03 register allocation map . . . . . . . . . .64
Table 70. Soft reset DLP registers (address 00h to 01h)
Table 71. FORCE_LOCK register (address 02h) bit
Table 72. Manual lock registers (address 03h to 04h)
Table 73. CA_CTRL register (address 05h) bit
Table 74. SCR_CNTRL register (address 06h) bit
Table 75. ILA_CTRL register (address 07h) bit
Table 76. FORCE_ALIGN register (address 08h) bit
Table 77. Manual alignment registers (address 09h
Table 78. FA_ERR_HANDLING register (address 0Bh)
Table 79. SYNCOUT_MODE register (address 0Ch) bit
Table 80. LANE_POLARITY register (address 0Dh) bit
Table 81. LANE_SELECT register (address 0Eh) bit
Table 82. SOFT_RESET_SCRAMBLER register
Table 83. Initialization values registers (address 11h
Table 84. ERROR_HANDLING register (address 1Bh)
Table 85. REINIT_CTRL register (address 1Ch) bit
Table 86. MISC_CTRL register (address 1Dh) bit
DAC1628D1G25
Objective data sheet
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
bit description . . . . . . . . . . . . . . . . . . . . . . . . .60
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
bit description . . . . . . . . . . . . . . . . . . . . . . . . .62
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
bit description . . . . . . . . . . . . . . . . . . . . . . . . .66
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
bit description . . . . . . . . . . . . . . . . . . . . . . . . .67
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
to 0Ah) bit description . . . . . . . . . . . . . . . . . . .70
bit description . . . . . . . . . . . . . . . . . . . . . . . . .70
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
(address 10h) bit description . . . . . . . . . . . . . .73
to 1Ah) bit description . . . . . . . . . . . . . . . . . . .73
bit description . . . . . . . . . . . . . . . . . . . . . . . . .74
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Table 87. LMF_CTRL register (address 1Eh) bit
Table 88. PAGE_ADDRESS register (address 1Fh)
Table 89. Page x04 register allocation map . . . . . . . . . . 77
Table 90. ILA_MON registers (address 00h to 01h) bit
Table 91. ILA_BUFF_ERR register (address 02h) bit
Table 92. CA_MON register (address 03h) bit
Table 93. DEC_FLAGS register (address 04h) bit
Table 94. KOUT_FLAG register (address 05h) bit
Table 95. K28 FLAG registers (address 06h to 09h) bit
Table 96. KOUT_UNEXPECTED_FLAG register
Table 97. LOCK_CNT_MON registers (address 0Bh
Table 98. CS_STATE_LNX register (address 0Dh) bit
Table 99. RST_BUF_ERR_FLAGS register (address
Table 100. INTR_MISC_ENA register (address 0Fh)
Table 101. LSB/MSB of flag_counter lane registers
Table 102. LSB/MSB BER measurement registers
Table 103. INTR_ENA register (address 1Ah) bit
Table 104. CTRL_FLAGCNT registers (address 1Bh
Table 105. MON_FLAGS_RESET register (address 1Dh)
Table 106. DBG_CNTRL register (address 1Eh) bit
Table 107. PAGE_ADDRESS register (address 1Fh)
Table 108. Counter source . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 109. Code group synchronization state machine . . 86
Table 110. Page x08 register allocation map . . . . . . . . . . 88
Table 111. Lane 0 configuration registers (address 00h
Table 112. Lane 1/lane 0 sample LSB/MSB registers
Table 113. Lane 1 configuration registers (address 10h
Table 114. LN10_SELECT register (address 1Eh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 75
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
(address 0Ah) bit description . . . . . . . . . . . . . 82
to 0Ch) bit description . . . . . . . . . . . . . . . . . . . 82
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
0Eh) bit description . . . . . . . . . . . . . . . . . . . . . 82
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 82
(address 10h to 17h) bit description . . . . . . . . 83
(address 18h to 19h) bit description . . . . . . . . 83
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
to 1Ch) bit description . . . . . . . . . . . . . . . . . . . 84
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 84
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 85
to 0Dh) bit description . . . . . . . . . . . . . . . . . . . 91
(address 0Eh to 0Fh) bit description . . . . . . . . 92
to 1Dh) bit description . . . . . . . . . . . . . . . . . . . 92
DAC1628D1G25
© NXP B.V. 2011. All rights reserved.
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