dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 2

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
2. Features and benefits
DAC1628D1G25
Objective data sheet
The DAC1628D1G25 includes a 2, 4 or 8 clock multiplier which provides the
appropriate internal clocks and an internal regulation to adjust the full-scale output
current. The internal PLL can be bypassed to achieve the best possible noise
performance at the analog outputs. The internal regulator adjusts the full-scale output
current between 8.1 mA and 34 mA.
The device is available in a HVQFN56 package (8 mm  8 mm). It is supported by
customer demo boards that are supplied with or without FPGA logic devices.
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Dual channel 16-bit resolution
1.25 Gsps maximum output update rate
JEDEC JESD204B device subclass I
compliant: SYSREF based deterministic
and repeatable interface latency
Multiple Device Synchronization (MDS,
a unique CGVxpress feature) enables
up to 16 DAC channels to be sample
synchronous and phase coherent to
within one DAC clock period
1, 2 or 4 configurable JESD204B serial
input lanes running up to 6.25 Gbps with
embedded termination and
programmable equalization
625 Msps maximum baseband input
data rate
SPI interface (3-wire or 4-wire mode) for
control setting and status monitoring
Differential scalable output current from
8.1 mA to 34 mA
Embedded NCO with 40-bit
programmable frequency and 16-bit
phase adjustment
Embedded complex (IQ) digital
modulator
1.8 V and 3.3 V power supplies
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
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SFDR
(f
bandwidth = 250 MHz; f
NSD = 164 dBm/Hz typical
(f
IMD3 = 85 dBc typical (f
interpolation 4; f
f
One carrier ACLR = 77 dB typical
(f
RF enable/disable pin and RF automatic
mute
Very low noise bypassable integrated
Phase-Locked Loop (PLL); no external
capacitors
External analog offset control (10-bit
auxiliary DACs)
power-down mode and sleep mode
controls
On-chip 1.25 V reference
Industrial temperature range
40 C to +85 C
HVQFN56 package (8 mm  8 mm)
o2
s
o
s
= 1.22 Gsps; interpolation 4;
= 1.22 Gsps; f
= 20 MHz)
= 155.1 MHz)
RBW
DAC1628D1G25
= 85 dBc typical
NCO
o1
= 152 MHz;
= 210 MHz)
© NXP B.V. 2011. All rights reserved.
out
s
= 1.22 Gsps;
= 150 MHz)
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