dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 97

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 117. Lane 2 configuration registers (address 10h to 1Dh) bit description
Default settings are shown highlighted.
DAC1628D1G25
Objective data sheet
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
10.17.6.4 Page x09 bit definition detailed description
Register
LN2_CFG_0
LN2_CFG_2
LN2_CFG_2
LN2_CFG_3
LN2_CFG_4
LN2_CFG_5
LN2_CFG_6
LN2_CFG_7
LN2_CFG_8
LN2_CFG_9
LN2_CFG_10
LN2_CFG_11
LN2_CFG_12
LN2_CFG_13
The tables in this section contain detailed descriptions of the page x09 registers.
Bit
7 to 0
7 to 4
3 to 0
6
5
4 to 0
7
4 to 0
7 to 0
4 to 0
7 to 0
7 to 6
4 to 0
7 to 5
4 to 0
7 to 5
4 to 0
7
4 to 0
7 to 0
7 to 0
7 to 0
Symbol
LN2_DID[7:0]
LN2_ADJCNT[3:0]
LN2_BID[3:0]
LN2_ADJDIR
LN2_PHADJ
LN2_LID[4:0]
LN2_SCR
LN2_L[4:0]
LN2_F[7:0]
LN2_K[4:0]
LN2_M[7:0]
LN2_CS[1:0]
LN2_N[4:0]
LN2_SUBCLASSV[2:0]
LN2_N’[4:0]
LN2_JESDV
LN2_S[4:0]
LN2_HD
LN2_CF[4:0]
LN2_RES1[7:0]
LN2_RES2[7:0]
LN2_FCHK[7:0]
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Access Value
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
00
01
10
-
-
000
001
-
-
-
-
-
-
DAC1628D1G25
Description
lane 2 device ID
lane 2 adjustable counter
lane 2 bank ID
lane 2 adjustable direction
lane 2 adjustable phase
lane 2 lane ID
scrambling on
number of lanes minus 1
number of octets per frame
minus 1
number of frames per
multi-frame minus 1
number of converters per
device minus 1
number of control bits
converter resolution minus 1
lane 2 JSED204B subclass
version
number of bits per sample
minus 1
Lane 2 JESD204 version
number of samples per
converter per frame cycle
minus 1
high density
number of control words per
frame cycle
lane 2 reserved field
lane 2 reserved field
lane 2 checksum
subclass 0
subclass 1
subclass 2
version A
version B
© NXP B.V. 2011. All rights reserved.
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