UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 760

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

760
3rd edition
Edition
Modification of oscillation frequency range X1 oscillator and external main system
clock in 6.1 (1) Main system clock
Addition to description in 6.1 (3) Internal low-speed oscillation clock
Modification of Figure 6-1 Block Diagram of Clock Generator
Modification of Figure 6-3 Format of Processor Clock Control Register (PCC)
Addition of 6.3 (3) Setting of operation mode for subsystem clock pin
Modification of description in 6.3 (8) Oscillation stabilization time select register
(OSTS)
Modification of oscillation frequency range in 6.4.1 X1 oscillator
Modification of description in 6.4.3 When subsystem clock is not used
Addition of Figure 6-12 Clock Generator Operation When Power Supply Voltage
Is Turned On (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0))
Addition of Figure 6-13 Clock Generator Operation When Power Supply Voltage
Is Turned On (When 2.7 V/1.59 V POC Mode Is Set (Option Byte: POCMODE =
1))
Modification of 6.6.1 Controlling high-speed system clock
Modification of 6.6.2 Example of controlling internal high-speed oscillation
clock
Modification of 6.6.3 Example of controlling subsystem clock
Modification of description in Table 6-4 Clocks Supplied to CPU and Peripheral
Hardware, and Register Setting
Addition of Remark to Figure 6-14 CPU Clock Status Transition Diagram (When
1.59 V POC Mode Is Set (Option Byte: POCMODE = 0))
Modification of the following items in Table 6-5 CPU Clock Transition and SFR
Register Setting Examples
(3) CPU operating with subsystem clock (D) after reset release (A)
(4) CPU clock changing from internal high-speed oscillation clock (B) to high-
(5) CPU clock changing from internal high-speed oscillation clock (B) to
(7) CPU clock changing from high-speed system clock (C) to subsystem clock
(9) CPU clock changing from subsystem clock (D) to high-speed system clock
Modification of Table 6-6 Changing CPU Clock
Addition of 6.6.8 Time required for switchover of CPU clock and main system
clock
Addition of 6.6.9 Conditions before clock oscillation is stopped
Addition of 6.6.10 Peripheral Hardware and Source Clocks
speed system clock (C)
subsystem clock (D)
(D)
(C)
APPENDIX E REVISION HISTORY
User’s Manual U17260EJ6V0UD
Description
CHAPTER 6 CLOCK
GENERATOR
Chapter
(4/16)