UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 748

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

748
Reset
function
Power-
on-clear
circuit
Low-
voltage
detector
Function
Block diagram of
reset function
Watchdog timer
overflow
RESF: Reset
control flag
register
In 2.7 V/1.59 V
POC mode
Cautions for
power-on-clear
circuit
LVIM: Low-
voltage detection
register
LVIS: Low-
voltage detection
level selection
register
When detecting
level of supply
voltage (V
When detecting
level of input
voltage from
external input pin
(EXLVI)
Details of
Function
−
−
DD
)
To stop LVI, follow either of the procedures below.
• When using 8-bit memory manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
For an external reset, input a low level for 10
During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock,
and internal low-speed oscillation clock stop oscillating. External main system
clock input and external subsystem clock input become invalid.
When the STOP mode is released by a reset, the STOP mode contents are held
during reset input. However, the port pins become high-impedance, except for
P130, which is set to low-level output.
An LVI circuit internal reset does not reset the LVI circuit.
A watchdog timer internal reset resets the watchdog timer.
Do not read data by a 1-bit memory manipulation instruction.
If an internal reset signal is generated in the POC circuit, the reset control flag
register (RESF) is cleared to 00H.
Set the low-voltage detector by software after the reset status is released (see
CHAPTER 24 LOW-VOLTAGE DETECTOR).
A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the power
supply voltage reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V
(TYP.) to 2.7 V (TYP.) within 1.93 ms, the power supply oscillation stabilization
time of 0 to 5.39 ms is automatically generated before reset processing.
In a system where the supply voltage (V
vicinity of the POC detection voltage (V
and released from the reset status. In this case, the time from release of reset to
the start of the operation of the microcontroller can be arbitrarily set by taking the
following action.
Input voltage from external input pin (EXLVI) must be EXLVI < V
After an LVI reset has been generated, do not write values to LVIS and LVIM when
LVION = 1.
When using LVI as an interrupt, if LVION is cleared (0) in a state below the LVI
detection voltage, an INTLVI signal is generated and LVIIF becomes 1.
Be sure to clear bits 4 to 7 to “0”.
Do not change the value of LVIS during LVI operation.
When an input voltage from the external input pin (EXLVI) is detected, the
detection voltage (V
necessary.
After an LVI reset has been generated, do not write values to LVIS and LVIM when
LVION = 1.
<1> must always be executed. When LVIMK = 0, an interrupt may occur
immediately after the processing in <4>.
If supply voltage (V
reset signal is not generated.
<1> must always be executed. When LVIMK = 0, an interrupt may occur
immediately after the processing in <3>.
If input voltage from external input pin (EXLVI) ≥ detection voltage (V
(TYP.)) when LVIMD is set to 1, an internal reset signal is not generated.
Input voltage from external input pin (EXLVI) must be EXLVI < V
APPENDIX D LIST OF CAUTIONS
User’s Manual U17260EJ6V0UD
DD
EXLVI
) ≥ detection voltage (V
= 1.21 V (TYP.)) is fixed. Therefore, setting of LVIS is not
Cautions
POC
DD
) fluctuates for a certain period in the
), the system may be repeatedly reset
LVI
µ
s or more to the RESET pin.
) when LVIMD is set to 1, an internal
DD
DD
.
.
EXLVI
= 1.21 V
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