UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 502

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

<R>
(1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H)
502
Notes 1.
INTAD
INTSR0
INTWTI
INTTM51
INTKR
INTWT
INTP6
INTP7
INTIIC0
INTDMU
INTCSI11
INTTM001
INTTM011
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or
upon reset signal generation.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt
routine is entered.
IF0L, IF0H, IF1L, and IF1H are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H, and
IF1L and IF1H are combined to form 16-bit registers IF0 and IF1, they are set by a 16-bit memory manipulation
instruction.
Reset signal generation sets these registers to 00H.
Interrupt
Source
2.
3.
4.
5.
6.
Note 2
Note 2, 3
Note 1
Note 3
Note 3
Note 3
When 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated upon
the timing when the INTTM5H1 signal is generated (see Figure 9-13 Transfer Timing).
Do not use serial interface IIC0 and multiplier/divider simultaneously, because the flags corresponding to
the interrupt request sources of serial interface IIC0 and multiplier/divider support both of these interrupt
request sources. If software which operates serial interface IIC0 is developed by CC78K0 which is C
compiler, do not select the check box of “Using Multiplier/Divider” on GUI of PM+.
µ
If either interrupt source INTIIC0 or INTDMU is generated, bit 0 of IF1H is set (1).
Bit 0 of MK1H supports both interrupt sources INTIIC0 and INTDMU.
Bit 0 of PR1H supports both interrupt sources INTIIC0 and INTDMU.
PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D only.
ADIF
SRIF0
WTIIF
TMIF51
KRIF
WTIF
PIF6
PIF7
IICIF0
DMUIF
CSIIF11
TMIF001
TMIF011
Table 19-2. Flags Corresponding to Interrupt Request Sources (2/2)
Interrupt Request Flag
Note 4
Note 3, 4
Note 3
Note 3
Note 3
CHAPTER 19 INTERRUPT FUNCTIONS
IF1H
IF1L
Register
User’s Manual U17260EJ6V0UD
ADMK
SRMK0
WTIMK
TMMK51
KRMK
WTMK
PMK6
PMK7
IICMK0
DMUMK
CSIMK11
TMMK001
TMMK011
Note 5
Interrupt Mask Flag
Note 3, 5
Note 3
Note 3
Note 3
MK1H
MK1L
Register
ADPR
SRPR0
WTIPR
TMPR51
KRPR
WTPR
PPR6
PPR7
IICPR0
DMUPR
CSIPR11
TMPR001
TMPR011
Priority Specification Flag
Note 6
Note 3, 6
Note 3
Note 3
Note 3
PR1L
PR1H
Register