UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 414

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UPD78F0537DGA(T)-9EV-A

Manufacturer Part Number
UPD78F0537DGA(T)-9EV-A
Description
8BIT MCU, 128K FLASH, 7KB RAM, SMD
Manufacturer
NEC
Datasheet

Specifications of UPD78F0537DGA(T)-9EV-A

Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
(5) SO1n output (see Figures 16-1 and 16-2)
414
The status of the SO1n output is as follows if bit 7 (CSIE1n) of serial operation mode register 1n (CSIM1n) is
cleared to 0.
Notes 1.
Caution If a value is written to TRMD1n, DAP1n, and DIR1n, the output value of SO1n changes.
Remark
TRMD1n = 0
TRMD1n = 1
TRMD1n
2.
n = 0:
n = 0, 1:
The actual output of the SO10/P12 or SO11/P02 pin is determined according to PM12 and P12
or PM02 and P02, as well as the SO1n output.
Status after reset
Note 2
µ
µ
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
PD78F0531, 78F0532, 78F0533
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
DAP1n = 0
DAP1n = 1
DAP1n
Table 16-3. SO1n Output Status
User’s Manual U17260EJ6V0UD
DIR1n = 0
DIR1n = 1
DIR1n
Outputs low level
Value of SO1n latch
(low-level output)
Value of bit 7 of SOTB1n
Value of bit 0 of SOTB1n
SO1n Output
Note 2
Note 1

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