UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 339

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE0) of asynchronous serial
Cautions 1. To start the transmission, set POWER0 to 1 and then set TXE0 to 1. To stop the transmission,
Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2)
interface reception error status register 0 (ASIS0) is not set and the error interrupt does not occur.
2. To start the reception, set POWER0 to 1 and then set RXE0 to 1. To stop the reception, clear
3. Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin. If
4. TXE0 and RXE0 are synchronized by the base clock (f
5. Set transmit data to TXS0 at least one base clock (f
6. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits.
7. Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with
8. Be sure to set bit 0 to 1.
PS01
clear TXE0 to 0, and then clear POWER0 to 0.
RXE0 to 0, and then clear POWER0 to 0.
POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception is started.
transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after
TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock,
the transmission circuit or reception circuit may not be initialized.
“number of stop bits = 1”, and therefore, is not affected by the set value of the SL0 bit.
CL0
SL0
0
0
1
1
0
1
0
1
Character length of data = 7 bits
Character length of data = 8 bits
Number of stop bits = 1
Number of stop bits = 2
PS00
0
1
0
1
CHAPTER 14 SERIAL INTERFACE UART0
Does not output parity bit.
Outputs 0 parity.
Outputs odd parity.
Outputs even parity.
User’s Manual U17260EJ6V0UD
Transmission operation
Specifies character length of transmit/receive data
Specifies number of stop bits of transmit data
XCLK0
) after setting TXE0 = 1.
Reception without parity
Reception as 0 parity
Judges as odd parity.
Judges as even parity.
XCLK0
) set by BRGC0.
Reception operation
Note
To enable
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