UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 728

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

728
Memory
bank
switching
function
( µ PD78F0536,
78F0537,
78F0537D
only)
Port
function
Function
BANK: Memory
bank select
register
Memory bank
P02/SO11,
P04/SCK11
P10/SCK10/TxD0,
P12/SO10
Port 2
P31/INTP2/
OCD1A
P121/X1/OCD0A,
P122/X2/EXCLK/
OCD0B, P123/XT1,
P124/XT2/EXCLKS
Port mode
registers
ADPC: A/D port
configuration
register
Details of
Function
Be sure to change the value of the BANK register in the common area (0000H to
7FFFH). If the value of the BANK register is changed in the bank area (8000H to
BFFFH), an inadvertent program loop occurs in the CPU. Therefore, never
change the value of the BANK register in the bank area.
Instructions cannot be fetched between different memory banks.
Branching and accessing cannot be directly executed between different memory
banks. Execute branching or accessing between different memory banks via the
common area.
Allocate interrupt servicing in the common area.
An instruction that extends from 7FFFH to 8000H can only be executed in
memory bank 0.
To use P02/SO11 and P04/SCK11 as general-purpose ports, set serial operation
mode register 11 (CSIM11) and serial clock selection register 11 (CSIC11) to the
default status (00H).
To use P10/SCK10/TxD0 and P12/SO10 as general-purpose ports, set serial
operation mode register 10 (CSIM10) and serial clock selection register 10
(CSIC10) to the default status (00H).
Make the AV
digital port.
In the product with an on-chip debug function (
P31/INTP2/OCD1A pin down before a reset release, to prevent malfunction.
For products without an on-chip debug function and with the flash memory of 48
KB or more (
product rank of “I”, “K”, or “E”, and for the product with an on-chip debug function
(
memory with a flash programmer.
• P31/INTP2/OCD1A: Connect to EV
The above connection is not necessary when writing the flash memory by means
of self programming.
When using the P121 to P124 pins to connect a resonator for the main system
clock (X1, X2) or subsystem clock (XT1, XT2), or to input an external clock for the
main system clock (EXCLK) or subsystem clock (EXCLKS), the X1 oscillation
mode, XT1 oscillation mode, or external clock input mode must be set by using
the clock operation mode select register (OSCCTL) (for details, see 6.3 (1) Clock
operation mode select register (OSCCTL) and (3) Setting of operation mode for
subsystem clock pin). The reset value of OSCCTL is 00H (all of the P121 to P124
pins are I/O port pins). At this time, setting of the PM121 to PM124 and P121 to
P124 pins is not necessary.
For products without an on-chip debug function and with the flash memory of 48
KB or more (
product rank of “I”, “K”, or “E”, and for the product with an on-chip debug function
(
memory with a flash programmer.
• P121/X1/OCD0A: When using this pin as a port, connect it to V
The above connection is not necessary when writing the flash memory by means
of self programming.
Be sure to set bit 7 of PM0, bits 4 to 7 of PM3, bits 4 to 7 of PM4, bits 4 to 7 of
PM5, bits 4 to 7 of PM6, bits 5 to 7 of PM12, and bits 2 to 7 of PM14 to “1”.
Set the channel used for A/D conversion to the input mode by using port mode
register 2 (PM2).
If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC
when the CPU is operating on the subsystem clock and the peripheral hardware
clock is stopped. For details, see CHAPTER 35 CAUTIONS FOR WAIT.
µ
µ
PD78F0537D), connect P31/INTP2/OCD1A as follows when writing the flash
PD78F0537D), connect P121/X1/OCD0A as follows when writing the flash
APPENDIX D LIST OF CAUTIONS
µ
µ
REF
User’s Manual U17260EJ6V0UD
PD78F0534, 78F0535, 78F0536, and 78F0537) and having a
PD78F0534, 78F0535, 78F0536, and 78F0537) and having a
pin the same potential as the V
(10 kΩ: recommended) (in the input mode) or leave it open
(in the output mode).
Cautions
SS
via a resistor (10 kΩ: recommended).
µ
DD
PD78F0537D), be sure to pull the
pin when port 2 is used as a
SS
via a resistor
p. 93
p. 94
p. 94
p. 94
p. 94
p. 105
p. 111
p. 116
p. 117
p. 117
p. 125
p. 125
p. 131
p. 134
p. 134
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