UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 435

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

17.5 I
Figure 17-12 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the
I
The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device
that receives 8-bit data).
level period can be extended and a wait can be inserted.
17.5.1 Start conditions
The start conditions for the SCL0 pin and SDA0 pin are signals that the master device generates to the slave device
when starting a serial transfer. When the device is used as a slave, start conditions can be detected.
been detected (SPD0: Bit 0 = 1 in IIC status register 0 (IICS0)). When a start condition is detected, bit 1 (STD0) of
IICS0 is set (to 1).
2
C bus’s serial data bus.
The following section describes the I
The master device generates the start condition, slave address, and stop condition.
The serial clock (SCL0) is continuously output by the master device. However, in the slave device, the SCL0’s low
A start condition is met when the SCL0 pin is at high level and the SDA0 pin changes from high level to low level.
A start condition is output when bit 1 (STT0) of IIC control register 0 (IICC0) is set (to 1) after a stop condition has
2
C Bus Definitions and Control Methods
SDA0
SCL0
Start
condition
Figure 17-12. I
Address R/W ACK
1-7
SDA0
SCL0
CHAPTER 17 SERIAL INTERFACE IIC0
2
C bus’s serial data communication format and the signals used by the I
Figure 17-13. Start Conditions
8
H
User’s Manual U17260EJ6V0UD
2
C Bus Serial Data Transfer Timing
9
Data
1-8
ACK
9
Data
1-8
ACK
9
Stop
condition
2
C bus.
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