UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 522

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Notes 1. When the CPU is operating on the subsystem clock and the internal high-speed oscillation clock has been
Remark f
522
Item
System clock
CPU
Flash memory
RAM
Port (latch)
16-bit timer/event
counter
8-bit timer/event
counter
8-bit timer
Watch timer
Watchdog timer
Clock output
Buzzer output
A/D converter
Serial interface
Multiplier/divider
Power-on-clear function
Low-voltage detection function
External interrupt
Main system clock
Subsystem clock
f
RL
2.
µ
f
f
f
f
f
stopped, do not start operation of these functions on the external clock input from peripheral hardware pins.
RH
X
EXCLK
XT
EXCLKS
RL
PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D only.
HALT Mode Setting
:
:
:
:
Note2
:
: External subsystem clock
UART0
UART6
CSI10
CSI11
IIC0
Internal high-speed oscillation clock
X1 clock
External main system clock
XT1 clock
Internal low-speed oscillation clock
00
01
50
51
H0
H1
Note1
f
f
f
f
f
RH
X
EXCLK
XT
EXCLKS
Note1
Notes1, 2
Note1
Notes1. 2
Note1
Note1
Clock supply to the CPU is stopped
Status before HALT mode was set is retained
Operates or stops by external clock input
Operation continues (cannot be stopped)
Operates or stops by external clock input
Status before HALT mode was set is retained
Operation stopped
Operation stopped
Status before HALT mode was set is retained
Status before HALT mode was set is retained
Operable
Operable. Clock supply to watchdog timer stops when “internal low-speed oscillator can be
stopped by software” is set by option byte.
Operable
Operable. However, operation disabled when peripheral hardware clock (f
Operable
Table 21-1. Operating Statuses in HALT Mode (2/2)
When CPU Is Operating on XT1 Clock (f
When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock
CHAPTER 21 STANDBY FUNCTION
User’s Manual U17260EJ6V0UD
XT
)
Status before HALT mode was set is retained
Operation continues (cannot be stopped)
When CPU Is Operating on External
Subsystem Clock (f
PRS
) is stopped.
EXCLKS
)