UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 439

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

17.5.6 Wait
receive data (i.e., is in a wait state).
canceled for both the master and slave devices, the next data transfer can begin.
The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or
Setting the SCL0 pin to low level notifies the communication partner of the wait state. When wait state has been
(1) When master device has a nine-clock wait and slave device has an eight-clock wait
(master transmits, slave receives, and ACKE0 = 1)
Transfer lines
Master
Slave
ACKE0
SDA0
SCL0
SCL0
SCL0
IIC0
IIC0
H
D2
CHAPTER 17 SERIAL INTERFACE IIC0
6
6
Master returns to high
impedance but slave
is in wait state (low level).
Wait after output
of eighth clock
D1
7
7
User’s Manual U17260EJ6V0UD
Figure 17-18. Wait (1/2)
D0
8
8
Wait from slave
9
ACK
Wait after output
of ninth clock
9
FFH is written to IIC0 or WREL0 is set to 1
Wait from master
IIC0 data write (cancel wait)
D7
1
1
D6
2
2
D5
3
3
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