UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 737

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

A/D
converter
Function
A/D conversion
timer selection
ADCR: 10-bit A/D
conversion
register
ADCRH: 8-bit
A/D conversion
register
ADS: Analog
input channel
specification
register
ADS: Analog
input channel
specification
register,
ADPC: A/D port
configuration
register
ADPC: A/D port
configuration
register
Basic operations
of A/D converter
A/D conversion
operation
Operating current
in STOP mode
Details of
Function
If data is read from ADCRH, a wait cycle is generated. Do not read data from
ADCRH when the CPU is operating on the subsystem clock and the peripheral
hardware clock is stopped. For details, see CHAPTER 35 CAUTIONS FOR
WAIT.
If data is written to ADS, a wait cycle is generated. Do not write data to ADS when
the CPU is operating on the subsystem clock and the peripheral hardware clock is
stopped. For details, see CHAPTER 35 CAUTIONS FOR WAIT.
When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D
conversion once (ADCS = 0) beforehand.
Change LV1 and LV0 from the default value, when 2.3 V ≤ AV
The above conversion time does not include clock frequency errors. Select
conversion time, taking clock frequency errors into consideration.
When writing to the A/D converter mode register (ADM), analog input channel
specification register (ADS), and A/D port configuration register (ADPC), the
contents of ADCR may become undefined. Read the conversion result following
conversion completion before writing to ADM, ADS, and ADPC. Using timing
other than the above may cause an incorrect conversion result to be read.
If data is read from ADCR, a wait cycle is generated. Do not read data from
ADCR when the CPU is operating on the subsystem clock and the peripheral
hardware clock is stopped. For details, see CHAPTER 35 CAUTIONS FOR
WAIT.
When writing to the A/D converter mode register (ADM), analog input channel
specification register (ADS), and A/D port configuration register (ADPC), the
contents of ADCRH may become undefined. Read the conversion result following
conversion completion before writing to ADM, ADS, and ADPC. Using timing
other than the above may cause an incorrect conversion result to be read.
Be sure to clear bits 3 to 7 to “0”.
Set a channel to be used for A/D conversion in the input mode by using port mode
register 2 (PM2).
If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC
when the CPU is operating on the subsystem clock and the peripheral hardware
clock is stopped. For details, see CHAPTER 35 CAUTIONS FOR WAIT.
Make sure the period of <1> to <5> is 1
Make sure the period of <1> to <5> is 1
<1> may be done between <2> and <4>.
<1> can be omitted. However, ignore data of the first conversion after <5> in this
case.
The period from <6> to <9> differs from the conversion time set using bits 5 to 1
(FR2 to FR0, LV1, LV0) of ADM. The period from <8> to <9> is the conversion
time set using FR2 to FR0, LV1, and LV0.
The A/D converter stops operating in the STOP mode. At this time, the operating
current can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D
converter mode register (ADM) to 0. To restart from the standby status, clear bit 0
(ADIF) of interrupt request flag register 1L (IF1L) to 0 and start operation.
APPENDIX D LIST OF CAUTIONS
User’s Manual U17260EJ6V0UD
Cautions
µ
µ
s or more.
s or more.
REF
< 2.7 V.
p. 317
p. 317
p. 317
p. 318
p. 318
p. 319
p. 319
p. 320
p. 320
pp. 320,
321
p. 321
p. 323
p. 327
p. 327
p. 327
p. 327
p. 330
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