UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 364

no-image

UPD78F0537DGA(T)-9EV-A

Manufacturer Part Number
UPD78F0537DGA(T)-9EV-A
Description
8BIT MCU, 128K FLASH, 7KB RAM, SMD
Manufacturer
NEC
Datasheet

Specifications of UPD78F0537DGA(T)-9EV-A

Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
(2) Asynchronous serial interface reception error status register 6 (ASIS6)
364
Address: FF53H After reset: 00H R
Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of
Symbol
ASIS6
This register indicates an error status on completion of reception by serial interface UART6. It includes three
error flag bits (PE6, FE6, OVE6).
This register is read-only by an 8-bit memory manipulation instruction.
Reset signal generation, or clearing bit 7 (POWER6) or bit 5 (RXE6) of ASIM6 to 0 clears this register to 00H.
00H is read when this register is read. If a reception error occurs, read ASIS6 and then read receive buffer
register 6 (RXB6) to clear the error flag.
Figure 15-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6)
2. For the stop bit of the receive data, only the first stop bit is checked regardless of the number
3. If an overrun error occurs, the next receive data is not written to receive buffer register 6
4. If data is read from ASIS6, a wait cycle is generated. Do not read data from ASIS6 when the
OVE6
PE6
FE6
asynchronous serial interface operation mode register 6 (ASIM6).
of stop bits.
(RXB6) but discarded.
CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 35 CAUTIONS FOR WAIT.
7
0
0
1
0
1
0
1
If POWER6 = 0 or RXE6 = 0, or if ASIS6 register is read
If the parity of transmit data does not match the parity bit on completion of reception
If POWER6 = 0 or RXE6 = 0, or if ASIS6 register is read
If the stop bit is not detected on completion of reception
If POWER6 = 0 or RXE6 = 0, or if ASIS6 register is read
If receive data is set to the RXB6 register and the next reception operation is completed before the
data is read.
6
0
CHAPTER 15 SERIAL INTERFACE UART6
5
0
User’s Manual U17260EJ6V0UD
Status flag indicating framing error
Status flag indicating overrun error
Status flag indicating parity error
4
0
3
0
PE6
2
FE6
1
OVE6
0

Related parts for UPD78F0537DGA(T)-9EV-A