UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 171

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B)
(7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
(8) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B)
Status Transition
(C) → (B)
Status Transition
(C) → (D) (XT1 clock)
(C) → (D) (external subsystem clock)
Status Transition
(D) → (B)
Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14.
2. MCM0:
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
EXCLKS, OSCSELS: Bits 5 and 4 of the clock operation mode select register (OSCCTL)
RSTS, RSTOP:
XTSTART, CSS:
×:
Table 6-5. CPU Clock Transition and SFR Register Setting Examples (3/4)
Setting Flag of SFR Register
Setting Flag of SFR Register
Setting Flag of SFR Register
Bits 7 and 0 of the internal oscillation mode register (RCM)
Bits 6 and 4 of the processor clock control register (PCC)
Bit 0 of the main clock mode register (MCM)
Don’t care
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17260EJ6V0UD
Unnecessary if the CPU is operating
XTSTART
with the internal high-speed oscillation clock
RSTOP
with the internal high-speed
0
1
0
Unnecessary if the CPU is operating
RSTOP
0
Unnecessary if the CPU is operating
oscillation clock
0
with the subsystem clock
EXCLKS
Confirm this flag
0
×
1
RSTS
is 1.
Confirm this flag is 1.
OSCSELS
RSTS
1
×
1
Unnecessary if
XSEL is 0
MCM0
0
↑
Unnecessary
Stabilization
Waiting for
Necessary
Oscillation
MCM0
0
CSS
0
CSS
1
1
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