UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 425

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Cautions concerning set timing
• For master reception:
• For master transmission: A stop condition cannot be generated normally during the acknowledge period. Therefore, set it
• Cannot be set to 1 at the same time as STT0.
• SPT0 can be set to 1 only when in master mode
• When WTIM0 has been cleared to 0, if SPT0 is set to 1 during the wait period that follows output of eight clocks, note that a
• Setting SPT0 to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (SPT0 = 0)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
Note Set SPT0 to 1 only in master mode. However, SPT0 must be set to 1 and a stop condition generated before
Caution When bit 3 (TRC0) of IIC status register 0 (IICS0) is set to 1, WREL0 is set to 1 during the ninth
Remark
stop condition will be generated during the high-level period of the ninth clock. WTIM0 should be changed from 0 to 1 during
the wait period following the output of eight clocks, and SPT0 should be set to 1 during the wait period that follows the output
of the ninth clock.
SPT0
0
1
the first stop condition is detected following the switch to the operation enabled status. For details, see
17.5.15 Other cautions.
Stop condition is not generated.
Stop condition is generated (termination of master device’s transfer).
After the SDA0 line goes to low level, either set the SCL0 line to high level or wait until it goes to high level. Next,
after the rated amount of time has elapsed, the SDA0 line changes from low level to high level and a stop
condition is generated.
clock and wait is canceled, after which TRC0 is cleared and the SDA0 line is set to high
impedance.
Bit 0 (SPT0) becomes 0 when it is read after data setting.
Cannot be set to 1 during transfer.
Can be set to 1 only in the waiting period when ACKE0 has been cleared to 0 and slave has been
notified of final reception.
during the wait period that follows output of the ninth clock.
Figure 17-5. Format of IIC Control Register 0 (IICC0) (4/4)
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17260EJ6V0UD
Note
.
Stop condition trigger
Condition for setting (SPT0 = 1)
• Set by instruction
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