UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 149

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UPD78F0537DGA(T)-9EV-A

Manufacturer Part Number
UPD78F0537DGA(T)-9EV-A
Description
8BIT MCU, 128K FLASH, 7KB RAM, SMD
Manufacturer
NEC
Datasheet

Specifications of UPD78F0537DGA(T)-9EV-A

Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
(6) Main clock mode register (MCM)
This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware
clock.
MCM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: FFA1H
Symbol
MCM
Note Bit 1 is read-only.
Cautions 1. XSEL can be changed only once after a reset release.
XSEL
MCS
7
0
0
0
1
1
0
1
After reset: 00H
2. A clock other than f
Figure 6-6. Format of Main Clock Mode Register (MCM)
Operates with internal high-speed oscillation clock
Operates with high-speed system clock
regardless of the setting of XSEL and MCM0.
• Watchdog timer (operates with internal low-speed oscillation clock)
• When “f
• Peripheral hardware selects the external clock as the clock source
MCM0
(operates with internal low-speed oscillation clock)
(Except when the external count clock of TM0n (n = 0, 1) is selected (TI00n pin
valid edge))
6
0
0
1
0
1
R/W
CHAPTER 6 CLOCK GENERATOR
Internal high-speed oscillation clock
(f
High-speed system clock (f
RL
RH
”, “f
Selection of clock supplied to main system clock and peripheral hardware
)
Note
User’s Manual U17260EJ6V0UD
5
0
RL
Main system clock (f
/2
7
”, or “f
PRS
4
0
Main system clock status
RL
is supplied to the following peripheral functions
/2
9
” is selected as the count clock for 8-bit timer H1
XH
XP
)
)
3
0
Internal high-speed oscillation clock
(f
High-speed system clock (f
RH
XSEL
Peripheral hardware clock (f
)
<2>
MCS
<1>
XH
)
MCM0
<0>
PRS
)
149

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