UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 539

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UPD78F0537DGA(T)-9EV-A

Manufacturer Part Number
UPD78F0537DGA(T)-9EV-A
Description
8BIT MCU, 128K FLASH, 7KB RAM, SMD
Manufacturer
NEC
Datasheet

Specifications of UPD78F0537DGA(T)-9EV-A

Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
22.1 Register for Confirming Reset Source
store which source has generated the reset request.
Many internal reset generation sources exist in the 78K0/KE2. The reset control flag register (RESF) is used to
RESF can be read by an 8-bit memory manipulation instruction.
RESET input, reset by power-on-clear (POC) circuit, and reading RESF set RESF to 00H.
The status of RESF when a reset request is generated is shown in Table 22-3.
Address: FFACH
Symbol
RESF
Flag
WDTRF
LVIRF
Note The value after reset varies depending on the reset source.
Caution Do not read data by a 1-bit memory manipulation instruction.
WDTRF
LVIRF
7
0
0
1
0
1
After reset: 00H
Reset Source
Table 22-3. RESF Status When Reset Request Is Generated
Figure 22-5. Format of Reset Control Flag Register (RESF)
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
6
0
Note
Cleared (0)
RESET Input
CHAPTER 22 RESET FUNCTION
R
User’s Manual U17260EJ6V0UD
5
0
Internal reset request by low-voltage detector (LVI)
Internal reset request by watchdog timer (WDT)
WDTRF
Cleared (0)
Reset by POC
4
3
0
Set (1)
Held
Reset by WDT
2
0
Held
Set (1)
Reset by LVI
1
0
LVIRF
0
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