UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 401

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(3) Port mode registers 0 and 1 (PM0, PM1)
Cautions 1. Do not write to CSIC11 while CSIE11 = 1 (operation enabled).
Remark f
These registers set port 0 and 1 input/output in 1-bit units.
When using P10/SCK10 and P04/SCK11
to 0, and set the output latches of P10 and P04 to 1.
When using P12/SO10 and P02/SO11
the output latches of P12 and P02 to 0.
When using P10/SCK10 and P04/SCK11
P03/SI11
PM03, and PM05 to 1. At this time, the output latches of P10, P04, P11, P03, and P05 may be 0 or 1.
PM0 and PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Note Available only in the
Note
2. To use P02/SO11 and P04/SCK11 as general-purpose ports, set CSIC11 in the default status
3. The phase type of the data clock is type 1 after reset.
PRS
as the data input pins, and P05/SSI11
: Peripheral hardware clock frequency
(00H).
Address: FF20H
Symbol
Address: FF21H
Symbol
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
µ
Figure 16-7. Format of Port Mode Register 0 (PM0)
Figure 16-8. Format of Port Mode Register 1 (PM1)
PM0
PM1
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
PM17
PM0n
PM1n
7
1
7
0
1
0
1
Note
PM06
PM16
Output mode (output buffer on)
Input mode (output buffer off)
Output mode (output buffer on)
Input mode (output buffer off)
Note
User’s Manual U17260EJ6V0UD
6
6
as the data output pins of the serial interface, clear PM12, PM02, and
Note
After reset: FFH
After reset: FFH
as the clock output pins of the serial interface, clear PM10 and PM04
P0n pin I/O mode selection (n = 0 to 6)
P1n pin I/O mode selection (n = 0 to 7)
as the clock input pins of the serial interface, P11/SI10/R
PM05
PM15
5
5
Note
PM04
PM14
/TI001 as the chip select input pin, set PM10, PM04, PM11,
4
4
PM03
PM13
R/W
R/W
3
3
PM02
PM12
2
2
PM01
PM11
1
1
PM00
PM10
0
0
X
D0 and
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