UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 628

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UPD78F0537DGA(T)-9EV-A

Manufacturer Part Number
UPD78F0537DGA(T)-9EV-A
Description
8BIT MCU, 128K FLASH, 7KB RAM, SMD
Manufacturer
NEC
Datasheet

Specifications of UPD78F0537DGA(T)-9EV-A

Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
<R>
<R>
Notes 1.
Note C is the load capacitance of the SO1n output line.
Remark n = 0:
628
SCK1n cycle time
SCK1n high-/low-level width
SI1n setup time (to SCK1n↑)
SI1n hold time (from SCK1n↑)
Delay time from SCK1n↓ to
SO1n output
SCK1n cycle time
SCK1n high-/low-level width
SI1n setup time (to SCK1n↑)
SI1n hold time (from SCK1n↑)
Delay time from SCK1n↓ to
SO1n output
(d) CSI1n (master mode, SCK1n... internal clock output)
(e) CSI1n (slave mode, SCK1n... external clock input)
2.
n = 0, 1:
Parameter
Parameter
This value is when high-speed system clock (f
C is the load capacitance of the SCK1n and SO1n output lines.
µ
µ
PD78F0531, 78F0532, 78F0533
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
t
t
t
t
t
t
t
t
t
t
t
t
KCY1
KH1
KL1
SIK1
KSI1
KSO1
KCY2
KH2
KL2
SIK2
KSI2
KSO2
Symbol
Symbol
,
,
C = 50 pF
User’s Manual U17260EJ6V0UD
4.0 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
4.0 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
4.0 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
C = 50 pF
DD
DD
DD
DD
DD
DD
DD
DD
DD
Note
Note 2
Conditions
Conditions
≤ 5.5 V
< 4.0 V
< 2.7 V
≤ 5.5 V
< 4.0 V
< 2.7 V
≤ 5.5 V
< 4.0 V
< 2.7 V
4.0 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
XH
) is used.
DD
DD
DD
≤ 5.5 V
< 4.0 V
< 2.7 V
t
t
t
KCY1
KCY1
KCY1
t
15
25
50
KCY2
MIN.
MIN.
160
250
500
170
400
55
80
30
80
50
Note 1
Note 1
Note 1
/2 −
/2 −
/2 −
/2
TYP.
TYP.
Standard products
MAX.
MAX.
120
120
165
40
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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