UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 538

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Notes 1.
538
Serial interfaces CSI10,
CSI1
Serial interface IIC0
Multiplier/divider
Key interrupt
Reset function
Low-voltage detector
Interrupt
Note 2
2.
3.
4.
During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
Serial interface CSI11 is available only in the
78F0537D.
Multiplier/divider is available only in the
These values vary depending on the reset source.
Register
RESF
LVIM
LVIS
Note 3
Table 22-2. Hardware Statuses After Reset Acknowledgment (3/3)
Reset Source
Transmit buffer registers 10, 11 (SOTB10, SOTB11)
Serial I/O shift registers 10, 11 (SIO10, SIO11)
Serial operation mode registers 10, 11 (CSIM10, CSIM11)
Serial clock selection registers 10, 11 (CSIC10, CSIC11)
Shift register 0 (IIC0)
Control register 0 (IICC0)
Slave address register 0 (SVA0)
Clock selection register 0 (IICCL0)
Function expansion register 0 (IICX0)
Status register 0 (IICS0)
Flag register 0 (IICF0)
Remainder data register 0 (SDR0)
Multiplication/division data register A0 (MDA0H, MDA0L)
Multiplication/division data register B0 (MDB0)
Multiplier/divider control register 0 (DMUC0)
Key return mode register (KRM)
Reset control flag register (RESF)
Low-voltage detection register (LVIM)
Low-voltage detection level selection register (LVIS)
Request flag registers 0L, 0H, 1L, 1H (IF0L, IF0H, IF1L, IF1H)
Mask flag registers 0L, 0H, 1L, 1H (MK0L, MK0H, MK1L, MK1H)
Priority specification flag registers 0L, 0H, 1L, 1H (PR0L, PR0H, PR1L,
PR1H)
External interrupt rising edge enable register (EGP)
External interrupt falling edge enable register (EGN)
WDTRF bit
LVIRF bit
Cleared (0)
Cleared (00H)
RESET Input
CHAPTER 22 RESET FUNCTION
Hardware
User’s Manual U17260EJ6V0UD
µ
PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D.
Cleared (0)
Cleared (00H)
Reset by POC
µ
PD78F0534, 78F0535, 78F0536, 78F0537, and
Set (1)
Held
Cleared (00H)
Reset by WDT
Held
Set (1)
Held
Reset by LVI
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
0000H
0000H
0000H
00H
00H
00H
00H
00H
FFH
FFH
00H
00H
00H
Acknowledgment
Status After Reset
Note 4
Note 4
Note 4
Note 1