UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 743

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Serial
interface
CSI10,
CSI11
Serial
interface
IIC0
Function
SIO1n: Serial I/O shift
register 1n
CSIM10: Serial
operation mode
register 10
CSIC10: Serial clock
selection register 10
CSIC11: Serial clock
selection register 11
3-wire serial I/O mode Take relationship with the other party of communication when setting the port
Communication
operation
SO1n output
IIC0: IIC shift register
0
IICC0: IIC control
register 0
IICS0: IIC status
register 0
IICF0: IIC flag register
0
Selection clock setting Determine the transfer clock frequency of I
Details of Function
−
Do not access SIO1n when CSOT1n = 1 (during serial communication).
In the slave mode, reception is started when data is read from SIO11 with a low
level input to the SSI11 pin. For details on the reception operation, see 16.4.2
(2) Communication operation.
Be sure to clear bit 5 to 0.
Do not write to CSIC10 while CSIE10 = 1 (operation enabled).
To use P10/SCK10/T
in the default status (00H).
The phase type of the data clock is type 1 after reset.
Do not write to CSIC11 while CSIE11 = 1 (operation enabled).
To use P02/SO11 and P04/SCK11 as general-purpose ports, set CSIC11 in the
default status (00H).
The phase type of the data clock is type 1 after reset.
mode register and port register.
Do not access the control register and data register when CSOT1n = 1 (during
serial communication).
When using serial interface CSI11, wait for the duration of at least one clock
before the clock operation is started to change the level of the SSI11 pin in the
slave mode; otherwise, malfunctioning may occur.
If a value is written to TRMD1n, DAP1n, and DIR1n, the output value of SO1n
changes.
Do not use serial interface IIC0 and the multiplier/divider simultaneously,
because various flags corresponding to interrupt request sources are shared
among serial interface IIC0 and the multiplier/divider.
Do not write data to IIC0 during data transfer.
Write or read IIC0 only during the wait period. Accessing IIC0 in a
communication state other than during the wait period is prohibited. When the
device serves as the master, however, IIC0 can be written only once after the
communication trigger bit (STT0) is set to 1.
The start condition is detected immediately after I
(IICE0 = 1) while the SCL0 line is at high level and the SDA0 line is at low level.
Immediately after enabling I
1-bit memory manipulation instruction.
When bit 3 (TRC0) of IIC status register 0 (IICS0) is set to 1, WREL0 is set to 1
during the ninth clock and wait is canceled, after which TRC0 is cleared and the
SDA0 line is set to high impedance.
If data is read from IICS0, a wait cycle is generated. Do not read data from
IICS0 when the CPU is operating on the subsystem clock and the peripheral
hardware clock is stopped. For details, see CHAPTER 35 CAUTIONS FOR
WAIT.
Write to STCEN only when the operation is stopped (IICE0 = 0).
As the bus release status (IICBSY = 0) is recognized regardless of the actual
bus status when STCEN = 1, when generating the first start condition (STT0 =
1), it is necessary to verify that no third party communications are in progress in
order to prevent such communications from being destroyed.
Write to IICRSV only when the operation is stopped (IICE0 = 0).
CL00 before enabling the operation (by setting bit 7 (IICE0) of IIC control
register 0 (IICC0) to 1). To change the transfer clock frequency, clear IICE0
once to 0.
APPENDIX D LIST OF CAUTIONS
User’s Manual U17260EJ6V0UD
X
D0 and P12/SO10 as general-purpose ports, set CSIC10
2
C to operate (IICE0 = 1), set LREL0 (1) by using a
Cautions
2
C by using CLX0, SMC0, CL01, and
2
C is enabled to operate
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