UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 197
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UPD78F0537DGA(T)-9EV-A
Manufacturer Part Number
UPD78F0537DGA(T)-9EV-A
Description
8BIT MCU, 128K FLASH, 7KB RAM, SMD
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0537DGA(T)-9EV-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
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(a) 16-bit timer mode control register 0n (TMC0n)
(b) Capture/compare control register 0n (CRC0n)
(c) 16-bit timer output control register 0n (TOC0n)
(d) Prescaler mode register 0n (PRM0n)
(e) 16-bit timer counter 0n (TM0n)
(f) 16-bit capture/compare register 00n (CR00n)
(g) 16-bit capture/compare register 01n (CR01n)
Remark n = 0:
ES1n1
0
0
0
0
By reading TM0n, the count value can be read.
If M is set to CR00n, the interval time is as follows.
• Interval time = (M + 1) × Count clock cycle
Setting CR00n to 0000H is prohibited.
Usually, CR01n is not used for the interval timer function. However, a compare match interrupt (INTTM01n)
is generated when the set value of CR01n matches the value of TM0n.
Therefore, mask the interrupt request by using the interrupt mask flag (TMMK01n).
n = 0, 1:
OSPT0n
ES1n0
0
0
0
0
Figure 7-18. Example of Register Settings for Interval Timer Operation
µ
µ
OSPE0n
PD78F0531, 78F0532, 78F0533
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
ES0n1
0
0
0
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
TOC0n4
ES0n0
0
0
0
0
TMC0n3 TMC0n2 TMC0n1
LVS0n
1
0
User’s Manual U17260EJ6V0UD
0
3
0
CRC0n2 CRC0n1 CRC0n0
LVR0n
1
0
0
2
0
TOC0n1
PRM0n1 PRM0n0
0
0
0/1
0
OVF0n
0
0
TOE0n
0/1
0
Clears and starts on match
between TM0n and CR00n.
CR00n used as
compare register
Selects count clock
197
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