UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 341

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

<R>
(3) Baud rate generator control register 0 (BRGC0)
Address: FF71H After reset: 1FH R/W
BRGC0
Note 1. If the peripheral hardware clock (f
Symbol
This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter.
BRGC0 can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 1FH.
operating frequency varies depending on the supply voltage.
• V
• V
• V
MDL04
TPS01
TPS01
DD
DD
DD
7
0
0
1
1
0
0
0
0
1
1
1
1
1
1
•
•
•
•
•
= 4.0 to 5.5 V: f
= 2.7 to 4.0 V: f
= 1.8 to 2.7 V: f
Figure 14-4. Format of Baud Rate Generator Control Register 0 (BRGC0)
MDL03
TPS00
TPS00
6
0
1
0
1
0
1
1
1
•
•
•
•
•
1
1
1
1
1
1
PRS
PRS
PRS
CHAPTER 14 SERIAL INTERFACE UART0
TM50 output
f
f
f
PRS
PRS
PRS
≤ 20 MHz
≤ 10 MHz
≤ 5 MHz (Standard and (A) grade products only)
MDL02
/2
/2
/2
5
0
×
0
0
0
•
•
•
•
•
0
0
1
1
1
1
3
5
User’s Manual U17260EJ6V0UD
PRS
Note 2
) operates on the high-speed system clock (f
MDL04
MDL01
1 MHz
250 kHz
62.5 kHz
f
PRS
4
×
0
0
1
•
•
•
•
•
1
1
0
0
1
1
= 2 MHz
Base clock (f
MDL03
MDL00
3
×
0
1
0
•
•
•
•
•
0
1
0
1
0
1
2.5 MHz
625 kHz
156.25 kHz
f
PRS
XCLK0
= 5 MHz
) selection
10
26
27
28
29
30
31
k
×
8
9
•
•
•
•
•
MDL02
2
Setting prohibited
f
f
f
f
f
f
f
f
f
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
5 MHz
1.25 MHz
312.5 kHz
f
PRS
Selection of 5-bit counter
Note 1
/8
/9
/10
/26
/27
/28
/29
/30
/31
= 10 MHz
MDL01
output clock
1
•
•
•
•
•
XH
10 MHz
2.5 MHz
625 kHz
f
PRS
) (XSEL = 1), the f
= 20 MHz
MDL00
0
341
PRS