UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 169

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

<R>
(1) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
(2) CPU operating with high-speed system clock (C) after reset release (A)
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
(3) CPU operating with subsystem clock (D) after reset release (A)
(A) → (B)
Status Transition
(A) → (B) → (C) (X1 clock: 1 MHz ≤ f
10 MHz)
(A) → (B) → (C) (external main clock: 1 MHz ≤
f
(A) → (B) → (C) (X1 clock: 10 MHz < f
20 MHz)
(A) → (B) → (C) (external main clock: 10 MHz <
f
Status Transition
(A) → (B) → (D) (XT1 clock)
(A) → (B) → (D) (external subsystem clock)
XH
XH
Table 6-5 shows transition of the CPU clock and examples of setting the SFR registers.
Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14.
≤ 10 MHz)
≤ 20 MHz)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
CHAPTER 29
ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: T
2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH:
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
Status Transition
MSTOP:
XSEL, MCM0:
XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC)
×:
Table 6-5. CPU Clock Transition and SFR Register Setting Examples (1/4)
Setting Flag of SFR Register
Setting Flag of SFR Register
ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) to CHAPTER 32
XH
Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL)
Bit 7 of the main OSC control register (MOC)
Bits 2 and 0 of the main clock mode register (MCM)
Don’t care
XH
≤
≤
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17260EJ6V0UD
SFR registers do not have to be set (default status after reset release).
AMPH
XTSTART
0
0
1
1
0
1
0
EXCLK
0
1
0
1
EXCLKS
1
0
×
OSCSEL
1
1
1
1
SFR Register Setting
A
= −40 to +125°C)).
OSCSELS
MSTOP
0
0
0
0
1
×
1
Must not be
Must not be
checked
checked
Must be
Must be
Register
checked
checked
OSTC
Unnecessary
Stabilization
Waiting for
Necessary
Oscillation
XSEL
1
1
1
1
CSS
MCM0
1
1
1
1
1
1
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